Abstract: A quadrature amplitude modulator is provided. An oscillator generates an in-phase carrier signal having a rectangular wave, a trapezoidal wave or a waveform similar to these, and a quadrature carrier signal, the phase of which is shifted by ¼ cycle relative to the in-phase carrier signal. A multi-level driver generates an in-phase modulated signal by amplitude modulating the in-phase carrier signal with an analog in-phase baseband signal having a discrete voltage level or current level in accordance with the in-phase baseband data. Likewise, the multi-level driver generates a quadrature modulated signal by amplitude modulating the quadrature carrier signal with an analog quadrature baseband signal having a discrete voltage level or current level in accordance with the quadrature baseband data The multi-level driver generates a modulated signal, the amplitude of which takes a discrete level, by combining the modulated signals together.

Abstract: A test apparatus that tests a device under test, comprising a signal input section that supplies a test signal to a device under test and a judging section that judges acceptability of the device under test based on a response signal output by the device under test in response to the test signal. The signal input section includes an operation circuit that operates to generate the test signal and a power supply stabilizing circuit provided in the same chip to stabilize power supply voltage supplied to the operation circuit. The power supply stabilizing circuit includes a high-speed compensating section compensating for a change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed, and a low-speed compensating section compensating for the change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed lower than that of the high-speed compensating section.

Abstract: An equalizer circuit receives digital amplitude data A[N] which represents the amplitude level of the N-th (N is a nonnegative integer) signal to be transmitted via a transmission line and timing data T[N] which represents the cycle of the signal, and performs waveform shaping. The equalizer circuit includes: M (M is an integer) calculation units ECU1 through ECUM; and an adder ADD1 which adds the output data of the M calculation units ECU1 through ECUM and the amplitude data A[N] together so as to generate equalized amplitude data D[N]. A step response waveform RSTEP(t) for the transmission line is approximated by Expression RSTEP(t)=SSTEP(t)·(1?Sj=1:Mfj(t)) using M (M is an integer of 2 or more) functions fj(t) (1?j?M) and a step waveform SSTEP(t) with the time t as an argument. The representative value of the function fj(t) in a range between T1 and T2 is represented by a function gj(T1, T2).

Abstract: A quadrature amplitude demodulator demodulates a modulated signal on which quadrature amplitude modulation is performed. Oscillators generate an in-phase carrier signal having a rectangular wave, a trapezoidal wave or a waveform similar to these, and a quadrature carrier signal, the phase of which is shifted by ¼ cycle relative to the in-phase signal. First and second mixers respectively perform mixing of the modulated signal with the in-phase signal and the quadrature carrier signal. First and second integrators respectively integrate output signals of the first and the second mixers, for a predetermined period in accordance with the cycle of the in-phase carrier signal and the quadrature carrier signal. First and second A/D converters respectively convert outputs of the first and the second integrators into digital values.

Abstract: A cross-coupled inverter includes a first inverter and a second inverter cross-coupled such that the input terminal of each inverter is connected to the output terminal of the other inverter. A set signal is input to the gate of a first set transistor, and an inverted set signal is input to the gate of a fourth set transistor. A reset signal R is input to the gate of a first reset transistor of a reset unit, and an inverted reset signal is input to the gate of a fourth reset transistor thereof. The gate of the second set transistor and the gate of the third reset transistor are connected to the output terminal of the second inverter. The gate of the third set transistor and the gate of the second reset transistor are connected to the output terminal of the first inverter.

Abstract: A priority encoder encodes an (N+1)-bit thermometer code, where N indicates a natural number. A plurality of selectors are arranged in a matrix of M rows and (N+1) columns, where M indicates a natural number, and select one of signals at first and second input terminals (1,0) in accordance with the value of a signal input to the control terminal. An output signal from the selector in the i-th row and (j?1)th column is input to the first input terminal of the selector in the i-th row and j-th column (1?i?M, 2?j?N+1), a predetermined value of 1 or 0 is input to the second input terminal of the selector in the i-th row and j-th column, and the j-th significant bit of the thermometer code is input to the control terminal of the selector in the i-th row and j-th column.

Abstract: A voltage generator with current limiting generates a voltage to be fed to a load of which load current is limited. The voltage generator includes an operational amplifier; an output resistance connected between an output terminal of the operational amplifier and a load connecting terminal; a feedback resistor connected between the load connecting terminal and an inverting input terminal of the operational amplifier; a first clamper connected between the output terminal of the operational amplifier and the inverting input terminal of the operational amplifier; and a second clamper connected between the load connecting terminal and a non-inverting input terminal of the operational amplifier and configured with diodes. The first clamper generates a predetermined constant voltage, limits a current flowing into the output resistance, and varies the generated constant voltage. The first clamper has a predetermined abrupt current-voltage characteristic.

Abstract: A ring oscillator oscillates at a frequency determined by an input bias signal. A bias signal adjusting unit produces a bias signal for the ring oscillator using feedback so that the oscillation frequency of the ring oscillator matches a predetermined reference frequency. An individual bias circuit includes a plurality of bias circuits provided for a total of N second variable delay elements, respectively. The bias circuits are configured such that the bias signals can be individually adjusted.

Abstract: A first resistor is arranged such that a first voltage is applied to a first terminal thereof, and a second terminal thereof is connected to an input/output terminal. The first voltage is applied to a first terminal of a second resistor. A tail current source generates a predetermined tail current. A current switch receives data to be transmitted to a second device, selects one from among the second terminals of the first and second resistors, and connects the terminal thus selected to the tail current source. A voltage dividing circuit includes a third resistor and a fourth resistor provided in series between the second terminals of the first resistor and the second resistor. A load balancer includes a fifth resistor arranged such that a second voltage is applied to a first terminal thereof, and a second terminal thereof is connected to the second terminal of the second resistor.

Abstract: A comparison amplification unit compares a level of a signal in a positive line with that of a signal in a negative line and latches a comparison result. An input terminal of a first inverter is connected to the positive line and an output terminal thereof is connected to the negative line. An input terminal of a second inverter is connected to the negative line and an output terminal thereof is connected to the positive line. An activation switch selectively switches between a state where the activation switch outputs a power supply voltage to the other power supply terminals of the inverters that are connected in common, such that the comparison amplification unit is inactivated, and a state where the activation switch outputs the ground voltage such that the comparison amplification is activated. The comparator outputs a signal corresponding to at least one of the signal in the positive line and the signal in the negative line at a timing after the comparison amplification unit is activated.

Abstract: A main driver amplifier generates first differential signals (Vdp/Vdn) based on pattern data (PAT). A replica driver amplifier generates second differential signals (Vcp/Vcn) based on the pattern data (PAT). Two subtractors generate electric potential difference signals (HP=RP?Vep) and (HN=RN?Ven), respectively. Two sample hold circuits sample the electric potential difference signals (HP and HN), and hold them thereafter, respectively. A comparison unit compares a differential amplitude signal (DA=HHP?HHN) with a predetermined threshold value (VOH). A latch circuit latches an output from the comparison unit. Sampling timings of the two sample hold circuits and a latch timing of the latch circuit, can be adjusted independently.

Abstract: A power source stabilization circuit provided within a chip of an electronic device is provided. The power source stabilization circuit stabilizes a power source voltage supplied to an operational circuit of the electronic device. The power source stabilization circuit includes an amplifier that detects a fluctuation component in the power source voltage occurring in a main power source wiring used to supply the power source voltage to the operational circuit, amplifies the detected fluctuation component, and outputs the amplified fluctuation component, and a stabilization capacitor that is provided between an output end of the amplifier and the main power source wiring and supplies to the main power source wiring a current to reduce fluctuation in the power source voltage occurring in the main power source wiring, in accordance with the output from the amplifier.

Abstract: A main driver amplifier generates first differential signals (Vdp/Vdn) based on pattern data (PAT). A replica driver amplifier generates second differential signals (Vcp/Vcn) based on the pattern data (PAT). Two subtractors generate electric potential difference signals (HP=RP?Vep) and (HN=RN?Ven), respectively. Two sample hold circuits sample the electric potential difference signals (HP and HN),and hold them thereafter, respectively. A comparison unit compares a differential amplitude signal (DA=HHP?HHN) with a predetermined threshold value (VOH). A latch circuit latches an output from the comparison unit. Sampling timings of the two sample hold circuits and a latch timing of the latch circuit, can be adjusted independently.

Abstract: A voltage generator with current limiting generates a voltage to be fed to a load of which load current is limited. The voltage generator includes an operational amplifier; an output resistance connected between an output terminal of the operational amplifier and a load connecting terminal; a feedback resistor connected between the load connecting terminal and an inverting input terminal of the operational amplifier; a first clamper connected between the output terminal of the operational amplifier and the inverting input terminal of the operational amplifier; and a second clamper connected between the load connecting terminal and a non-inverting input terminal of the operational amplifier and configured with diodes. The first clamper generates a predetermined constant voltage, limits a current flowing into the output resistance, and varies the generated constant voltage. The first clamper has a predetermined abrupt current-voltage characteristic.

Abstract: One of differential signals is inputted to a first input terminal. The other of the differential signals is inputted to a second input terminal. A first sample hold circuit samples the signal inputted to the first input terminal and hold it thereafter. A second sample hold circuit samples the signal inputted to the second input terminal and holds it thereafter. A comparison unit compares a signal corresponding to a difference between respective output signals from the first and the second sample hold circuits, with a predetermined threshold value. A latch circuit latches an output from the comparison unit. Sample timings of the first and the second sample hold circuits and a latch timing of the latch circuit can be adjusted independently.

Abstract: An image processing apparatus including: a generating section, operable to analyze compressed image data stored in an external memory and generate an analytic table indicative of a storage manner of the compressed image data; an internal memory, adapted to store the compressed image data therein; a storage section, operable to acquire at least a part of the compressed image data from the external memory and store the compressed image data in the internal memory with reference to the analytic table; a decoding section, operable to read and decode the compressed image data stored in the storage section, and rotate and then output the compressed image data as a rotated image data; and an updater, operable to update the analytic table in accordance with a decoding situation of the decoding section.

Abstract: A first signal processor performs predetermined signal processing on an input signal to provide a change to at least one of the characteristic values thereof. A second signal processor is provided in the subsequent stage of the first signal processor and performs predetermined signal processing on an output signal from the first signal processor to provide a change to a characteristic value thereof. An amount of change provided to the characteristic value of the signal by the second signal processor is dependent on a power supply voltage. An amount of change provided to the characteristic value of the signal by the first signal processor is configured to be adjustable. A control circuit monitors a power supply voltage supplied to the second signal processor and adjusts in accordance with the power supply voltage the amount of change provided to the characteristic value of the signal by the first signal processor.

Abstract: A pulse width measurement circuit 100 generates a time difference signal S2 that corresponds to the pulse width TH of the input pulse signal PULSE. A delay circuit 12 delays the input pulse signal PULSE by a predetermined amount ?d, and outputs a start signal SSTART. An inverter 10 inverts the input pulse signal PULSE, and outputs a stop signal SSTOP. A time measurement circuit 14 measures the time difference ? between a positive edge in the start signal SSTART and a positive edge in the stop signal SSTOP, and outputs a time difference signal S2 that corresponds to the time difference.

Abstract: A variable delay circuit delays a carrier signal having a predetermined frequency, and outputs a modulated signal. A delay setting unit sets a delay period for the variable delay circuit according to a data signal to be modulated. The delay setting unit assigns each symbol in the data signal to any one of positive edges and negative edges in the carrier signal, and sets a delay period for the variable delay circuit at the timing at which a positive edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the positive edge. Furthermore, the delay setting unit sets a delay period for the variable delay circuit at the timing at which a negative edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the negative edge.

Abstract: A variable delay circuit delays a carrier signal having a predetermined frequency, and outputs a modulated signal. A delay setting unit sets a delay period for the variable delay circuit according to a data signal to be modulated. The delay setting unit assigns each symbol in the data signal to any one of positive edges and negative edges in the carrier signal, and sets a delay period for the variable delay circuit at the timing at which a positive edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the positive edge. Furthermore, the delay setting unit sets a delay period for the variable delay circuit at the timing at which a negative edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the negative edge.