Patents by Inventor Shoji Kubono
Shoji Kubono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7463533Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: GrantFiled: November 29, 2006Date of Patent: December 9, 2008Assignee: Renesas Technology Corp.Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Patent number: 7283400Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: GrantFiled: September 19, 2005Date of Patent: October 16, 2007Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd., Hitachi Ulsi Systems Co., Ltd.Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Publication number: 20070076490Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: ApplicationFiled: November 29, 2006Publication date: April 5, 2007Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Patent number: 7072225Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: GrantFiled: June 29, 2005Date of Patent: July 4, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Patent number: 6999348Abstract: A nonvolatile semiconductor storage unit can prevent erratic sense operations in a sense latch circuit by adopting a single-end sensing system capable of reducing an area (decreasing the number of elements). There is provided a flash memory chip using the single-end sensing system and an NMOS gate sensing system together. In the single-end sensing system, the sense latch circuit is connected to one end of a global bit line to detect data on the global bit line corresponding to a threshold voltage for a memory cell. The NMOS gate sensing system uses an NMOSFET to receive data on the global bit line at a gate and drive a node for the sense latch circuit. The NMOSFET senses a sense voltage. The sense latch circuit is activated with a sufficient signal quantity ensured. An output voltage from a threshold voltage applying power supply precharges the global bit line. In this manner, it is possible to always keep a constant difference between a precharge voltage and a threshold voltage for the NMOSFET.Type: GrantFiled: February 28, 2002Date of Patent: February 14, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Michitaro Kanamitsu, Yoshinori Takase, Shoji Kubono
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Patent number: 6992936Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: GrantFiled: February 12, 2004Date of Patent: January 31, 2006Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Publication number: 20060013032Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.Type: ApplicationFiled: September 19, 2005Publication date: January 19, 2006Inventors: Hideaki Kurata, Naoki Kobayashi, Shunichi Saeki, Takashi Kobayashi, Takayuki Kawahara, Yoshinori Takase, Keiichi Yoshida, Michitaro Kanamitsu, Shoji Kubono, Atsushi Nozoe
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Publication number: 20050237803Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: ApplicationFiled: June 29, 2005Publication date: October 27, 2005Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Patent number: 6930924Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: GrantFiled: April 2, 2003Date of Patent: August 16, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Publication number: 20050047212Abstract: A nonvolatile semiconductor storage unit can prevent erratic sense operations in a sense latch circuit by adopting a single-end sensing system capable of reducing an area (decreasing the number of elements). There is provided a flash memory chip using the single-end sensing system and an NMOS gate sensing system together. In the single-end sensing system, the sense latch circuit is connected to one end of a global bit line to detect data on the global bit line corresponding to a threshold voltage for a memory cell. The NMOS gate sensing system uses an NMOSFET to receive data on the global bit line at a gate and drive a node for the sense latch circuit. The NMOSFET senses a sense voltage. The sense latch circuit is activated with a sufficient signal quantity ensured. An output voltage from a threshold voltage applying power supply precharges the global bit line. In this manner, it is possible to always keep a constant difference between a precharge voltage and a threshold voltage for the NMOSFET.Type: ApplicationFiled: February 28, 2002Publication date: March 3, 2005Inventors: Michitaro Kanamitsu, Yoshinori Takase, Shoji Kubono
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Publication number: 20040228194Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: ApplicationFiled: June 22, 2004Publication date: November 18, 2004Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Publication number: 20040160829Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: ApplicationFiled: February 12, 2004Publication date: August 19, 2004Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6765840Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: GrantFiled: February 4, 2003Date of Patent: July 20, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Patent number: 6721207Abstract: A non-volatile memory system is provided with a control device and non-volatile memory devices, each including memory cells and data latches. The control device supplies commands to the non-volatile memory devices, including a write command, and first and second read commands. When the control device supplies the write command with write address information and data for storing in the non-volatile memory device, it stores the data to the data latches and then to the memory cells, and then verifies storage. When the control device supplies the first read command with read address information, the nonvolatile memory device reads data stored in the memory cells to the data latches and then outputs the data in the data latches to the control device. When the control device supplies the second read command, the non-volatile memory device outputs data in the data latches to the control device.Type: GrantFiled: August 5, 2002Date of Patent: April 13, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6711054Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: GrantFiled: November 19, 2002Date of Patent: March 23, 2004Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Publication number: 20030202392Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: ApplicationFiled: April 2, 2003Publication date: October 30, 2003Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Publication number: 20030128604Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: ApplicationFiled: February 4, 2003Publication date: July 10, 2003Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Patent number: 6567315Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.Type: GrantFiled: December 12, 2001Date of Patent: May 20, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Takase, Shoji Kubono, Michitaro Kanamitsu, Atsushi Nozoe, Keiichi Yoshida, Hideaki Kurata
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Patent number: 6567319Abstract: A semiconductor memory is designed to avoid a situation that the program cannot escape from a writing operation, and the writing operation can be promptly finished according to the level of an external source voltage. This semiconductor memory has a voltage detecting circuit for detecting whether a boosted voltage has reached a predetermined potential and a timer capable of counting predetermined time. A control circuit applies the boosted voltage to a selected memory cell when the voltage detecting circuit detects that the boosted voltage has reached the predetermined potential or when it is detected that the predetermined time has elapsed since the start of the boosting operation.Type: GrantFiled: June 17, 2002Date of Patent: May 20, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems, Co., Ltd.Inventors: Hiroshi Sato, Satoshi Noda, Kiichi Manita, Shoji Kubono, Koji Shigematsu
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Patent number: 6556499Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: GrantFiled: February 6, 2002Date of Patent: April 29, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Device Engineering Co., Ltd.Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto