Patents by Inventor Shoji Kubono
Shoji Kubono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020001207Abstract: For a semiconductor integrated circuit having an internal booster circuit such as a flash memory, voltage booster circuits capable of generating a boosted voltage 10 times or more as high as a relatively low source voltage is to be realized. Charge pumps for carrying out first stage voltage boosting on the basis of a source voltage are configured of parallel capacity type units, and charge pumps for carrying out second stage voltage boosting on the basis of the boosted voltage generated by the first charge pumps are configured of serial capacity type units.Type: ApplicationFiled: June 19, 2001Publication date: January 3, 2002Applicant: Hitachi, Ltd.Inventors: Jiro Kishimoto, Hiroshi Sato, Satoshi Noda, Tatsuya Ishii, Shoji Kubono, Takashi Ogino
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Patent number: 6333871Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: GrantFiled: March 30, 2000Date of Patent: December 25, 2001Assignee: Hitachi, Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6320793Abstract: A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the device according to the commands. The commands include read commands and write commands. In the read command the control circuit reads data in the memory cells and outputs it. In a write command the control circuit controls the inputting of data to data latch circuits and then to memory cells. The control circuit provides status information indicating whether the writing of data is a success or a failure.Type: GrantFiled: March 30, 2001Date of Patent: November 20, 2001Assignee: Hitachi, Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6301150Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: GrantFiled: April 28, 2000Date of Patent: October 9, 2001Assignee: Hitachi, Ltd.Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Patent number: 6285597Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: GrantFiled: November 29, 2000Date of Patent: September 4, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Publication number: 20010015909Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: ApplicationFiled: April 10, 2001Publication date: August 23, 2001Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Publication number: 20010010644Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: ApplicationFiled: March 30, 2001Publication date: August 2, 2001Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Publication number: 20010009520Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the over programming condition, the program data is no longer required to be again received from the external device.Type: ApplicationFiled: March 30, 2001Publication date: July 26, 2001Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6233174Abstract: A nonvolatile semiconductor memory device having a plurality of memory cells. Each cell stores data and has a threshold voltage corresponding to the data. A controller controls a partial erase operation in response to a command. This operation includes selecting memory cells in two groups, storing the data in a data latch, writing erase data indicating an erase state, erasing data of selected cells and programming the data stored in the data latch to selected memory cells and programming the erased data to selected memory cells.Type: GrantFiled: March 30, 2000Date of Patent: May 15, 2001Assignee: Hitachi, Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6222763Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: GrantFiled: February 3, 2000Date of Patent: April 24, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Device Engineering Co., Ltd.Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Publication number: 20010000023Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: ApplicationFiled: November 29, 2000Publication date: March 15, 2001Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Patent number: 6163485Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: GrantFiled: March 9, 2000Date of Patent: December 19, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Patent number: 6134148Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: GrantFiled: August 20, 1999Date of Patent: October 17, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Patent number: 6091640Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.Type: GrantFiled: September 30, 1997Date of Patent: July 18, 2000Assignees: Hitachi, Ltd., Hitachi ULSLI Engineering Corp.Inventors: Takayuki Kawahara, Hiroshi Sato, Atsushi Nozoe, Keiichi Yoshida, Satoshi Noda, Shoji Kubono, Hiroaki Kotani, Katsutaka Kimura
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Patent number: 6078519Abstract: Data are generated based on additional write data input to data latch circuits (DLR and DLL) and data read from memory cells (MC) to program non-volatile memory cells in a write state into the same write state and to program non-volatile memory cells in an erase state into a write state indicated by the additional write data. The generated data are latched in the data latch circuits to perform a logical synthesis process for additional writing. Even after the additional write operation, the logically synthesized data remain in the data latch circuits, and the latched data can be reused against abnormality in writing. This eliminates the need for receiving write data again from the outside when the additional write operation is to be retried.Type: GrantFiled: May 25, 1999Date of Patent: June 20, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Michitaro Kanamitsu, Tetsuya Tsujikawa, Toshinori Harada, Hiroaki Kotani, Shoji Kubono, Atsushi Nozoe, Takayuki Yoshitake
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Patent number: 6046936Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.Type: GrantFiled: February 16, 1999Date of Patent: April 4, 2000Assignee: Hitachi, Ltd.Inventors: Tetsuya Tsujikawa, Atsushi Nozoe, Michitaro Kanamitsu, Shoji Kubono, Eiji Yamamoto, Ken Matsubara
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Patent number: 6026014Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.Type: GrantFiled: December 19, 1997Date of Patent: February 15, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Device Engineering Co., Ltd.Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
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Patent number: 5598373Abstract: A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an inputType: GrantFiled: June 7, 1995Date of Patent: January 28, 1997Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Shoji Wada, Kanehide Kenmizaki, Masaya Muranaka, Masahiro Ogata, Hidetomo Aoyagi, Tetsuya Kitame, Masahiro Katayama, Shoji Kubono, Yukihide Suzuki, Makoto Morino, Sinichi Miyatake, Seiichi Shundo, Yoshihisa Koyama, Nobuhiko Ohno
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Patent number: 5272676Abstract: The self-refresh operation of one round of a RAM using dynamic memory cells is accomplished on the basis of the periodic pulses which are formed by an oscillating circuit substantially having no temperature dependency, and the self-refresh period is controlled by a timer circuit using a time constant circuit corresponding to the temperature dependency of the data storage in the memory cells. The operating voltage or boosted output voltage is monitored to switch the circuit operation for generating a plurality kinds of boosted voltages rising sequentially two and three times so that the boosted voltage may be a desired voltage. A control voltage to be fed to the gate of a MOSFET connected between the substrate and the earth potential of the circuit is generated by a dummy substrate voltage generator having a leakage current path varying to follow the fluctuations in a supply voltage.Type: GrantFiled: November 6, 1991Date of Patent: December 21, 1993Assignees: Hitachi, Ltd., Hitachivlsi Engineering Corp.Inventors: Shoji Kubono, Hiroshi Sato