Patents by Inventor Shoji Otaka
Shoji Otaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8060038Abstract: A radio transmitter including a combiner which combines input I/Q signals with feedback I/Q signals, a power amplifier which amplifies the quadrature modulated signal, a detector which detects amplitude and phase differences between the input and feedback I/Q signals, a switch to turn on and off the feedback I/Q signals, a generator to generate control signals which minimizes the amplitude difference and the phase difference, in a state where a transmission power is set, during for a period during which the switch is turned off, an amplitude adjuster which adjusts an amplitude of the feedback RF signal, during a period during which the switch is turned on, and a phase adjuster which adjusts a phase of the local signal, during the period during which the switch is turned on.Type: GrantFiled: August 7, 2008Date of Patent: November 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Otaka, Yuta Araki, Toru Hashimoto
-
Patent number: 7978486Abstract: A rectifier circuit includes an input terminal that receives an alternating-current signal, a first rectifier circuit that generates a first direct-current voltage from the alternating-current signal, a bias-voltage generating circuit that generates a bias voltage from the first direct-current voltage, and a second rectifier circuit that generates a second direct-current voltage from the alternating-current signal biased with the bias voltage.Type: GrantFiled: October 25, 2010Date of Patent: July 12, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Umeda, Shoji Otaka
-
Publication number: 20110116558Abstract: In one embodiment, a wireless transmission apparatus is disclosed. The apparatus includes a generator unit, an amplitude adjuster unit, a phase adjuster unit, and a setting unit. The generator unit generates an amplitude control signal that minimizes an amplitude difference and a phase control signal that minimizes a phase difference in a state in which a power is set during an OFF period of a switch. The amplitude adjuster unit adjusts an amplitude of a feedback RF signal according to the amplitude control signal during an ON period of the switch. The phase adjuster unit adjusts a phase of a local signal according to the phase control signal during the ON period. The setting unit sets, for a Cartesian loop, a first loop gain when the switch is OFF, and a second loop gain higher than the first loop gain when the switch is turned from OFF to ON.Type: ApplicationFiled: December 1, 2010Publication date: May 19, 2011Inventors: Shoji Otaka, Hiroaki Ishihara, Masahiro Hosoya, Osamu Watanabe, Kohei Onizuka
-
Patent number: 7911281Abstract: A PLL circuit includes: a voltage-controlled oscillator including: a first oscillating portion configured to generate first differential signals; and a second oscillating portion configured to generate second differential signals with a phase difference of 90 degrees from the first differential signals; a phase detector configured to compare phases of third differential signals based on the first and second differential signals with a phase of a reference signal; and a loop filter configured to generate a control voltage for controlling the voltage-controlled oscillator based on a result of the comparison in the phase detector.Type: GrantFiled: September 14, 2009Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroaki Hoshino, Osamu Watanabe, Shoji Otaka, Tetsuro Itakura
-
Patent number: 7904121Abstract: A trigger signal generating device includes a first power source terminal and a second power source terminal; a first current generator to generate a first current with a first amplitude in accordance with the amplitude of the input signal; a second current generator to generate a second current with a second amplitude, the second current being flowed from the first power source terminal to the second power source terminal; a current mirror circuit to amplify the second current generated from the second current generator to obtain an amplified current; and a trigger signal generator to convert the amplified current into a trigger signal used for triggering a trigger device, the voltage amplitude of the trigger signal being corresponding to the current amplitude of the amplified current; wherein both of the first and second current generators are connected to either one of the first and second power source terminals.Type: GrantFiled: October 23, 2007Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Umeda, Shoji Otaka
-
Publication number: 20110038191Abstract: A rectifier circuit includes an input terminal that receives an alternating-current signal, a first rectifier circuit that generates a first direct-current voltage from the alternating-current signal, a bias-voltage generating circuit that generates a bias voltage from the first direct-current voltage, and a second rectifier circuit that generates a second direct-current voltage from the alternating-current signal biased with the bias voltage.Type: ApplicationFiled: October 25, 2010Publication date: February 17, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshiyuki Umeda, Shoji Otaka
-
Patent number: 7876162Abstract: An amplifier includes: a substrate; first to fourth amplifying units arranged on the substrate and each having first and second terminals, and each amplifying first and second signals to generate first and second amplified signals; a first inductive line arranged on the substrate, connecting the first terminal of the first amplifying unit and the first terminal of the second amplifying unit, and having a linear portion and a bending portion; a second inductive line arranged on the substrate, connecting the second terminal of the second amplifying unit and the first terminal of the third amplifying unit, and having a linear portion and a bending portion; a third inductive line arranged on the substrate, connecting the second terminal of the third amplifying unit and the first terminal of the fourth amplifying unit, and having a linear portion and a bending portion; a fourth inductive line arranged on the substrate, connecting the second terminal of the fourth amplifying unit and the second terminal of the firsType: GrantFiled: September 14, 2009Date of Patent: January 25, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kohei Onizuka, Masahiro Hosoya, Hiroaki Ishihara, Shoji Otaka, Osamu Watanabe
-
Patent number: 7843709Abstract: A rectifier circuit includes an input terminal that receives an alternating-current signal, a first rectifier circuit that generates a first direct-current voltage from the alternating-current signal, a bias-voltage generating circuit that generates a bias voltage from the first direct-current voltage, and a second rectifier circuit that generates a second direct-current voltage from the alternating-current signal biased with the bias voltage.Type: GrantFiled: March 16, 2007Date of Patent: November 30, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Umeda, Shoji Otaka
-
Publication number: 20100237829Abstract: An assembled battery system includes an assembled battery including a plurality of electric cell blocks connected in series, the electric cell blocks each including at least one nonaqueous electrolyte secondary battery provided with a negative electrode current collector formed of aluminum or an aluminum alloy, a voltage measuring unit configured to measure a plurality of voltages of the electric cell blocks, a controller which controls charge/discharge of the assembled battery in accordance with the measured voltages, and bypass circuits connected in parallel to the electric cell blocks, the bypass circuits each bypassing a current that flows from a negative electrode of one of the electric cell blocks to a positive electrode of the one of electric cell blocks when the measured voltage of the one of electric cell blocks is a negative value not greater than a threshold value.Type: ApplicationFiled: March 18, 2010Publication date: September 23, 2010Inventors: Yoshinao TATEBAYASHI, Shoji Otaka, Tetsuro Itakura, Norio Takami
-
Publication number: 20100231431Abstract: An electronic system includes: an AC-DC converter to convert an AC voltage into a DC voltage and to supply the DC voltage to a secondary battery; a first detector to detect a remaining amount of the secondary battery; a transmitter to transmit a signal corresponding to the remaining amount of the secondary battery; a receiver to receive the signal transmitted by the transmitter; and a controller to control the AC-DC converter using the signal received by the receiver.Type: ApplicationFiled: September 15, 2009Publication date: September 16, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takafumi SAKAMOTO, Koji Ogura, Shoji Otaka, Toshiyuki Umeda, Tsuyoshi Kogawa, Manabu Mukai
-
Publication number: 20100225397Abstract: An amplifier includes: a substrate; first to fourth amplifying units arranged on the substrate and each having first and second terminals, and each amplifying first and second signals to generate first and second amplified signals; a first inductive line arranged on the substrate, connecting the first terminal of the first amplifying unit and the first terminal of the second amplifying unit, and having a linear portion and a bending portion; a second inductive line arranged on the substrate, connecting the second terminal of the second amplifying unit and the first terminal of the third amplifying unit, and having a linear portion and a bending portion; a third inductive line arranged on the substrate, connecting the second terminal of the third amplifying unit and the first terminal of the fourth amplifying unit, and having a linear portion and a bending portion; a fourth inductive line arranged on the substrate, connecting the second terminal of the fourth amplifying unit and the second terminal of the firsType: ApplicationFiled: September 14, 2009Publication date: September 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kohei Onizuka, Masahiro Hosoya, Hiroaki Ishihara, Shoji Otaka, Osamu Watanabe
-
Publication number: 20100215116Abstract: A wireless communication apparatus for performing communication using a first communication scheme which transmits a signal using amplitude shift keying and a second communication scheme which suppresses communication with others except a communication counterpart by transmitting a transmission suppression signal before communication is started. The apparatus includes: a first signal generation unit configured to generate transmission data; a modulation unit configured to generate first and second signals having different amplitudes by amplitude-shift keying the transmission data; a second signal generation unit configured to generate the transmission suppression signal having a signal length corresponding to that of the first signal; and a transmission unit configured to transmit the transmission suppression signal at the timing when the first signal is transmitted.Type: ApplicationFiled: September 15, 2009Publication date: August 26, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuyoshi KOGAWA, Kiyoshi Toshimitsu, Takafumi Sakamoto, Koji Ogura, Shoji Otaka, Toshiyuki Umeda
-
Publication number: 20100203851Abstract: A wireless transmission device includes an adding/subtracting unit configured to subtract a second signal and a third signal from a first signal to generate the second signal; a modulating unit configured to modulate the second signal to generate a fourth signal; a demodulating unit configured to demodulate the fourth signal to generate the third signal; and a transmitting unit configured to transmit the fourth signal.Type: ApplicationFiled: September 3, 2009Publication date: August 12, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroaki Ishihara, Masahiro Hosoya, Kohei Onizuka, Shoji Otaka, Osamu Watanabe
-
Publication number: 20100164633Abstract: A PLL circuit includes: a voltage-controlled oscillator including: a first oscillating portion configured to generate first differential signals; and a second oscillating portion configured to generate second differential signals with a phase difference of 90 degrees from the first differential signals; a phase detector configured to compare phases of third differential signals based on the first and second differential signals with a phase of a reference signal; and a loop filter configured to generate a control voltage for controlling the voltage-controlled oscillator based on a result of the comparison in the phase detector.Type: ApplicationFiled: September 14, 2009Publication date: July 1, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroaki Hoshino, Osamu Watanabe, Shoji Otaka, Tetsuro Itakura
-
Publication number: 20100164564Abstract: A starting apparatus includes: a storage unit storing an identifier; a rectifying unit rectifying a reception signal; a generating unit comparing the reception signal rectified in the rectifying unit to a reference signal and generating a digital signal from the reception signal; a judging unit judging whether or not the digital signal contains information of the identifier; a reference changing unit changing the reference signal when the judging unit judges that the reception signal does not contain information of the identifier; and a start instructing unit instructing start of an electric appliance when the judging unit judges that the reception signal contains information of the identifier.Type: ApplicationFiled: September 16, 2009Publication date: July 1, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shoji Otaka, Toshiyuki Umeda, Shigeyasu Iwata, Takafumi Sakamoto, Tsuyoshi Kogawa, Koji Ogura, Makoto Tsuruta, Yu Kaneko, Nobuhiko Sugasawa
-
Patent number: 7746120Abstract: A signal receiving device includes: a first conversion unit comprising a first input terminal to which a signal including a voltage signal and a reference voltage is inputted, and a first output terminal which output a first current signal voltage-current converted from the signal; a second conversion unit comprising a second input terminal to which the reference voltage is inputted, and a second output terminal which output a second current signal voltage-current converted from the reference voltage; a current mirror circuit comprising a third input terminal to which the second current signal is inputted, and a third output terminal which output a third current signal corresponding to the second current signal; and an output unit connected to both the first and third output terminals.Type: GrantFiled: January 26, 2009Date of Patent: June 29, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Umeda, Shoji Otaka
-
Publication number: 20100073222Abstract: An FMCW signal generator includes a frequency divider to divide the FMCW signal at a preset dividing ratio, a reference signal generator to periodically generate a reference signal at a second time interval not less than a loop time constant set for a PLL, a frequency of the reference signal being discretely swept within a range of fc±?f (fc is a center frequency, and ?f is a frequency sweep width) at a first time interval not more than the loop time constant, a comparison unit to compare the frequency divided signal with the reference signal to generate a comparison result signal corresponding to a phase difference between the frequency divided signal and the reference signal, a loop filter to filter the comparison result signal to generate a control voltage signal, and a VCO to have an oscillation frequency thereof controlled by the control voltage signal.Type: ApplicationFiled: March 20, 2009Publication date: March 25, 2010Inventors: Toshiya Mitomo, Hiroaki Hoshino, Osamu Watanabe, Shoji Otaka
-
Publication number: 20100056054Abstract: A method of setting a wireless link is provided between a first wireless device and a second wireless device in a wireless system. The first wireless device includes an extremely low-power receiver. When the extremely low-power receiver receives a predetermined wireless signal, the receiver turns on the first wireless device, and continues broadcast transmission of a packet periodically without a transmission pause until receiving a response packet from the second wireless device.Type: ApplicationFiled: August 18, 2009Publication date: March 4, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsumi Yamato, Takafumi Sakamoto, Toshiyuki Umeda, Shoji Otaka, Keisuke Mera, Hiroshi Nishimura, Hiroo Makari
-
Publication number: 20100039159Abstract: This control device includes: a rectifier to rectify a received signal; an amplifier having an amplifying element to amplify the signal rectified by the rectifier and an assisting element being connected to the amplifying element to assist the amplifying element; a determination unit to determine presence or absence of the signal amplified by the amplifier; and a controller to control the connection of the assisting element with the amplifying element at a predetermined timing.Type: ApplicationFiled: March 17, 2009Publication date: February 18, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shoji Otaka, Toshiyuki Umeda, Takafumi Sakamoto, Makoto Tsuruta, Keisuke Mera, Yu Kaneko
-
Patent number: 7663420Abstract: A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N?1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors.Type: GrantFiled: November 7, 2007Date of Patent: February 16, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yuta Araki, Shoji Otaka, Toru Hashimoto