Patents by Inventor Shoji Otaka

Shoji Otaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100037082
    Abstract: In a remote controller, a startup time or a first time duration until the startup time is input into an input unit. A timer unit counts a clock time or a second time duration. A control unit generates a signal to turn on an electrical apparatus when the second time duration reaches the first time duration, or when the clock time equals to the startup time. A transmitting unit transmits the signal. In the electrical apparatus, a main unit operates main function. A transformer supplies electricity from an external power source to the main unit through a switch. A rectifier rectifies the signal. A signal identifying unit identifies it. A reservation memory unit keeps parameter for main function. A control unit turns on the switch and controls the main unit according to the parameter when the signal is received. A battery supplies electricity to above units.
    Type: Application
    Filed: July 13, 2009
    Publication date: February 11, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takafumi SAKAMOTO, Toshiyuki Nakanishi, Makoto Tsuruta, Keisuke Mera, Toshiyuki Umeda, Shoji Otaka
  • Publication number: 20090302958
    Abstract: A digitally controlled oscillator includes a differential inductor including a positive terminal which outputs a positive-phase oscillation signal, a negative terminal which outputs a negative-phase oscillation signal, and a center tap, and including a first contact point in an arbitrary position between the positive terminal and the center tap, and a second contact point in a position corresponding to the first contact point between the negative terminal and the center tap, a first variable capacitor bank connected between the positive terminal and the negative terminal and including a plurality of first variable capacitors which switch capacitance between two values according to a first digital control code, and a second variable capacitor bank connected between the first contact point and the second contact point and including a plurality of second variable capacitors which switch capacitance between two values according to a second digital control code.
    Type: Application
    Filed: March 23, 2009
    Publication date: December 10, 2009
    Inventors: Hiroki Sakurai, Osamu Watanabe, Shoji Otaka, Ryoichi Tachibana
  • Publication number: 20090295434
    Abstract: A signal receiving device includes: a first conversion unit comprising a first input terminal to which a signal including a voltage signal and a reference voltage is inputted, and a first output terminal which output a first current signal voltage-current converted from the signal; a second conversion unit comprising a second input terminal to which the reference voltage is inputted, and a second output terminal which output a second current signal voltage-current converted from the reference voltage; a current mirror circuit comprising a third input terminal to which the second current signal is inputted, and a third output terminal which output a third current signal corresponding to the second current signal; and an output unit connected to both the first and third output terminals.
    Type: Application
    Filed: January 26, 2009
    Publication date: December 3, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiyuki UMEDA, Shoji OTAKA
  • Publication number: 20090234981
    Abstract: A receiving apparatus includes: a receiving unit receiving a set of a plurality of signals in which at least a part of transfer rates is different during a certain period of time; a rate detecting unit detecting a plurality of transfer rates of the plurality of signals; a first obtaining unit obtaining first information based on the plurality of transfer rates; a second obtaining unit obtaining second information based on the plurality of signals; and a control signal generating unit generating a control signal based on the first and second information.
    Type: Application
    Filed: December 10, 2008
    Publication date: September 17, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiyuki Umeda, Makoto Tsuruta, Shoji Otaka
  • Patent number: 7590400
    Abstract: In a radio apparatus, the band of a loop filter of a synthesizer in a blank channel searching state is narrower than the band in a communicating state. In addition, a radio wave environment is measured. A characteristic necessary for the radio apparatus is determined corresponding to the measured-radio wave environment. The power is controlled corresponding to the performance of the radio apparatus. Thus, the power consumption is decreased. In addition, the efficiency of the output power is improved. In the radio apparatus, the current consumption of a power amplifier PA is measured. A matching circuit (LNA or MIX) of the antenna is adjusted with the measured result so as to decrease an antenna loss. In the radio apparatus, a DC offset is removed from the transmitted power and the reflected wave. When the DC offset is removed using an AC coupling capacitor, the deterioration of the frequency characteristic of the receiving portion is compensated with a capacitor in a digital signal process.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: September 15, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoji Otaka, Hiroshi Tsurumi, Hiroshi Yoshida, Syuichi Sekine, Hiroyuki Kayano, Tadahiko Maeda
  • Publication number: 20090195353
    Abstract: A control device being a control device communicating with a controlled device to control the controlled device includes: a first memory to store first authentication information for authenticating the controlled device; a second memory to store second authentication information for making the controlled device authenticate itself; a determination unit to compare third authentication information sent from the controlled device for specifying the controlled device with the first authentication information; a calculator to perform calculation processing on the first authentication information or the third authentication information using the second authentication information to generate a calculated value; a transmitter to transmit, when the determination unit determines that the first authentication information and the third authentication information are the same, the calculated value to the controlled device; and a memory controller to update the first authentication information.
    Type: Application
    Filed: February 2, 2009
    Publication date: August 6, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki NAKANISHI, Takafumi Sakamoto, Keisuke Mera, Toshiyuki Umeda, Shoji Otaka, Yusuke Doi
  • Publication number: 20090199292
    Abstract: A control device communicating with a controlled device to control the controlled device includes a first memory to store first authentication information for activation of the controlled device, a second memory to store a key for encryption, a generator to generate third authentication information by encrypting second authentication information transmitted by the controlled device in response to the first authentication information using the key stored in the second memory, a transmitter to transmit the first authentication information or the third authentication information to the controlled device, and a memory controller to store the second authentication information or the third authentication information as first authentication information for next authentication in the first memory.
    Type: Application
    Filed: February 2, 2009
    Publication date: August 6, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takafumi SAKAMOTO, Keisuke Mera, Yusuke Doi, Toshiyuki Umeda, Shoji Otaka
  • Publication number: 20090184690
    Abstract: A charger includes: a rectifier to rectify a received radio wave to generate a charging current; a potential generator to generate a bias voltage setting an operating point of the rectifier; and a controller to supply the bias voltage generated by the potential generator when an output voltage of the rectifier is equal to or larger than a predetermined value.
    Type: Application
    Filed: January 15, 2009
    Publication date: July 23, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shoji OTAKA, Toshiyuki Umeda
  • Publication number: 20090132836
    Abstract: A power-saving control apparatus includes a memory storing first to Nth different authentication codes, determines, every time a signal including an authentication code is received, whether the authentication code in the received signal is a valid code which matches one of the authentication codes in the memory, outputs an operation signal to a main apparatus when the authentication code in the received signal is determined to be the valid code, and generates a new authentication code, when (a) the number of times the authentication code in each received signal matches a first authentication code of the authentication codes in the memory is equal to a predetermined value or (b) the authentication code in the received signal matches a second or subsequent authentication code of the authentication codes in the memory, to delete one of the authentication codes in the memory, and to store the new authentication code in the memory.
    Type: Application
    Filed: November 12, 2008
    Publication date: May 21, 2009
    Inventors: Keisuke Mera, Yusuke Doi, Takafumi Sakamoto, Toshiyuki Umeda, Shoji Otaka
  • Publication number: 20090111377
    Abstract: A frequency converter includes a voltage-current converter circuit which generates a positive-phase input current signal and a negative-phase input current signal, a switching circuit which switches between the positive-phase input current signal and the negative-phase input current signal according to a positive-phase local oscillator signal and a negative-phase local oscillator signal to generate a positive-phase output current signal and a negative-phase output current signal, an amplifier circuit which current-voltage converts and amplifies the positive-phase output current signal and negative-phase output current signal to generate a positive-phase output voltage signal and a negative-phase output voltage signal, and a plurality of CR circuits which are inserted at least either between the voltage-current converter circuit and the switching circuit or between the switching circuit and the amplifier circuit and each of which includes at least one capacitor through which high-frequency components pass and
    Type: Application
    Filed: September 22, 2008
    Publication date: April 30, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiya Mitomo, Rui Ito, Shoji Otaka
  • Publication number: 20090067356
    Abstract: A wireless communication device includes: a packet detection part detecting presence/absence of a reception of a packet; a judgment part judging whether or not temporal change of presence/absence of the reception of the packet detected in the packet detection part corresponds to a predetermined identifier; and a power source control unit controlling power supply from a power source based on a result of a judgment in the judgment part.
    Type: Application
    Filed: October 31, 2008
    Publication date: March 12, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takafumi SAKAMOTO, Kiyoshi Toshimitsu, Toshiyuki Umeda, Shoji Otaka, Keisuke Mera
  • Patent number: 7501892
    Abstract: An amplifier circuit according to the present invention comprises: a first differential amplifier circuit including a first transistor having a gate terminal forming a first input node, a second transistor having a gate terminal forming a second input node and having a dimensional ratio with respect to the first transistor of K:M (where K>M), and a first current source that supplies a first current to a source terminal of the first transistor and a source terminal of the second transistor; a second differential amplifier circuit including a third transistor having a gate terminal forming a third input node, a fourth transistor having a gate terminal forming a fourth input node and having a dimensional ratio with respect to the third transistor of M:K, and a second current source that supplies a second current to a source terminal of the third transistor and a source terminal of the fourth transistor, the second differential amplifier circuit having a same gain as the first differential amplifier circuit; a
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: March 10, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoji Otaka, Yuta Araki
  • Publication number: 20090052417
    Abstract: A wireless communication device includes: a detection part detecting presence/absence of a reception of a packet; a judgment part judging whether or not temporal change of presence/absence of the reception of the packet detected in the detection part corresponds to a predetermined identifier; and a power source control unit controlling a power source based on a result of a judgment in the judgment part.
    Type: Application
    Filed: February 29, 2008
    Publication date: February 26, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takafumi Sakamoto, Kiyoshi Toshimitsu, Toshiyuki Umeda, Shoji Otaka
  • Publication number: 20090046817
    Abstract: A receiving apparatus includes a unit detecting a specific-bit sequence included in a data sequence, a unit counting, as a count value n1, a first number of oscillations during a 1-bit-wide period of a first bit of the specific-bit sequence, and to count, as a count value n2, a second number of oscillations during a 1-bit-wide period of a second bit of the specific-bit sequence, a unit generating, when it is determined that the n1 is not less than the (n2?a) and is not more than the (n2+a) (a=1,2, . . . ), a timing of n1/2, fractions of which are carried, for the first bit to a third bit of the specific-bit sequence, and to generate a timing of n1 for a fourth bit and subsequent bits, and a unit acquiring a data sequence from the data sequence at the timing n1/2 and the timing n1.
    Type: Application
    Filed: July 24, 2008
    Publication date: February 19, 2009
    Inventors: Toshiyuki UMEDA, Shoji Otaka
  • Publication number: 20090042521
    Abstract: A radio transmitter including a combiner which combines input I/Q signals with feedback I/Q signals, a power amplifier which amplifies the quadrature modulated signal, a detector which detects amplitude and phase differences between the input and feedback I/Q signals, a switch to turn on and off the feedback I/Q signals, a generator to generate control signals which minimizes the amplitude difference and the phase difference, in a state where a transmission power is set, during for a period during which the switch is turned off, an amplitude adjuster which adjusts an amplitude of the feedback RF signal, during a period during which the switch is turned on, and a phase adjuster which adjusts a phase of the local signal, during the period during which the switch is turned on.
    Type: Application
    Filed: August 7, 2008
    Publication date: February 12, 2009
    Inventors: Shoji Otaka, Yuta Araki, Toru Hashimoto
  • Publication number: 20080311867
    Abstract: A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N?1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors.
    Type: Application
    Filed: February 4, 2008
    Publication date: December 18, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuta Araki, Shoji Otaka, Toru Hashimoto
  • Publication number: 20080238495
    Abstract: A frequency synthesizer includes a voltage-controlled oscillator to output an oscillation signal of a oscillating frequency in correspondence with a oscillation controlling voltage that is input to the oscillator, a first frequency-divider to subject the oscillation signal to frequency-division and output a first frequency signal, a second frequency-divider to subject the first frequency signal to frequency-division and output a second frequency signal, a controlling voltage generator to generate the oscillation controlling voltage corresponding to a phase difference between a reference clock signal and the second frequency signal, a frequency detector to detect a frequency difference between the second frequency signal and the reference clock signal, and a controller which controls a free-running frequency of the first frequency divider to minimize the frequency difference.
    Type: Application
    Filed: March 19, 2008
    Publication date: October 2, 2008
    Inventors: RYOICHI TACHIBANA, Shoji Otaka, Osamu Watanabe, Hiroaki Hoshino
  • Publication number: 20080204107
    Abstract: A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N?1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors.
    Type: Application
    Filed: November 7, 2007
    Publication date: August 28, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuta Araki, Shoji Otaka, Toru Hashimoto
  • Publication number: 20080100491
    Abstract: A trigger signal generating device includes a first power source terminal and a second power source terminal; a first current generator to generate a first current with a first amplitude in accordance with the amplitude of the input signal; a second current generator to generate a second current with a second amplitude, the second current being flowed from the first power source terminal to the second power source terminal; a current mirror circuit to amplify the second current generated from the second current generator to obtain an amplified current; and a trigger signal generator to convert the amplified current into a trigger signal used for triggering a trigger device, the voltage amplitude of the trigger signal being corresponding to the current amplitude of the amplified current; wherein both of the first and second current generators are connected to either one of the first and second power source terminals.
    Type: Application
    Filed: October 23, 2007
    Publication date: May 1, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiyuki Umeda, Shoji Otaka
  • Publication number: 20080080214
    Abstract: A rectifier circuit includes an input terminal that receives an alternating-current signal, a first rectifier circuit that generates a first direct-current voltage from the alternating-current signal, a bias-voltage generating circuit that generates a bias voltage from the first direct-current voltage, and a second rectifier circuit that generates a second direct-current voltage from the alternating-current signal biased with the bias voltage.
    Type: Application
    Filed: March 16, 2007
    Publication date: April 3, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiyuki Umeda, Shoji Otaka