Patents by Inventor Shoji Sakemi
Shoji Sakemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8557630Abstract: A challenge to be met by the present invention is to provide an electronic component mounting method and an electronic component mount structure that make it possible to assure bonding strength for an electronic component whose underside is provided with bumps. In electronic component mounting operation during which an electronic component (6) whose underside is provided with bumps (7) with solder is mounted on a substrate (1), a solder bonding material (3) including solder particles contained in a first thermosetting resin is used for bonding the bumps (7) to an electrode (2) formed on the substrate (1), thereby forming a solder bonding area (7*) where the solder particles and the bumps (7) are fused and solidified and a first resin reinforcement area (3a*) that reinforces the solder bonding area (7*).Type: GrantFiled: May 14, 2010Date of Patent: October 15, 2013Assignee: Panasonic CorporationInventor: Shoji Sakemi
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Publication number: 20120052633Abstract: A challenge to be met by the present invention is to provide an electronic component mounting method and an electronic component mount structure that make it possible to assure bonding strength for an electronic component whose underside is provided with bumps. In electronic component mounting operation during which an electronic component (6) whose underside is provided with bumps (7) with solder is mounted on a substrate (1), a solder bonding material (3) including solder particles contained in a first thermosetting resin is used for bonding the bumps (7) to an electrode (2) formed on the substrate (1), thereby forming a solder bonding area (7*) where the solder particles and the bumps (7) are fused and solidified and a first resin reinforcement area (3a*) that reinforces the solder bonding area (7*).Type: ApplicationFiled: May 14, 2010Publication date: March 1, 2012Applicant: PANASONIC CORPORATIONInventor: Shoji Sakemi
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Patent number: 7138034Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.Type: GrantFiled: June 21, 2002Date of Patent: November 21, 2006Assignees: Matsushita Electric Industrial Co., Ltd., Krosaki Harima CorporationInventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi, Taiji Matano, Nobuhiro Satou
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Patent number: 7074720Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion 18a formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member 17 for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion 18b formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.Type: GrantFiled: June 21, 2002Date of Patent: July 11, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi
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Patent number: 6852572Abstract: The method of manufacturing a semiconductor device of the present invention comprises: forming a resin layer on a surface of a semiconductor wafer on which a plurality of semiconductor elements are formed, forming through-holes on the resin layer, a first cutting of either the semiconductor wafer or the resin layer, mounting conductive balls on the through-hole, connecting the conductive ball to electrodes of the semiconductor element, and a second cutting for dividing the wafer into each piece of semiconductor devices. With the processes of the present invention, conductive balls can be easily and effectively mounted on a wafer under optimum conditions, without failure such as slipping or falling down from the required position. This fact contributes to an increased efficiency and a good productivity in the production of semiconductor devices.Type: GrantFiled: February 13, 2001Date of Patent: February 8, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Haji, Shoji Sakemi, Mitsuru Ozono, Tadahiko Sakai, Kiyoshi Arita
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Patent number: 6784112Abstract: A surface treatment method for thinning a silicon based substrate obtains a milky-dull color on an overall surface uniformly of the silicon based substrate. To be more specific, a surface opposite to a circuit-formed surface is mechanically polished, then the surface is etched using inert gas such as argon gas for producing plasma. This etching forms micro dimples uniformly on the surface. Next, the surface is further etched using fluorine based gas for producing plasma. This etching obtains a milky-dull color uniformly on the surface. As a result, printed marks on the surface can be read with ease, and pick-up errors in die-bonding can be reduced.Type: GrantFiled: April 3, 2002Date of Patent: August 31, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi
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Patent number: 6723651Abstract: A method of plasma processing a silicon-containing object to be processed at a high etching rate without causing a surface of the object to have a hazy appearance, so that this surface can have an excellent visual quality. In the plasma processing method of etching the surface of the semiconductor wafer, gas containing sulfur hexafluoride and helium is used as a plasma-generating gas. A fluorine radical as an active substance which reacts with silicon of the surface of the semiconductor wafer, gaseous silicon tetrafluoride yielded by the reaction and a compound (SFn) of fluorine and sulfur that is generated as a reaction product are removed by the helium gas functioning as carrier gas. The helium gas prevents the reaction product from adhering to the surface of the wafer again.Type: GrantFiled: January 7, 2002Date of Patent: April 20, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Shoji Sakemi
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Patent number: 6683379Abstract: A semiconductor device including a semiconductor substrate having a thickness of not more than 300 &mgr;m and a resin layer formed on a face thereof. A plurality of conductor sections formed in and through the resin layer, and a plurality of electrodes located on the resin layer and connected by the conductor sections to electrodes of semiconductor elements located on the substrate. The resin layer includes at least one of silica, alumina, zirconia, quartz fiber, glass fiber resin fiber and inorganic particles capable of absorbing ionic impurities.Type: GrantFiled: January 11, 2002Date of Patent: January 27, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Haji, Shoji Sakemi
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Patent number: 6617675Abstract: A semiconductor device assembly and a semiconductor device are provided which both can ensure reliability after a mounting process. The semiconductor device includes a semiconductor element equipped with bumps on an electrode patterned surface thereof for external connection. In the semiconductor device mounted on a substrate in the semiconductor device assembly, a semiconductor element shaped to have a thickness ranging from 200 &mgr;m to 10 &mgr;m has reduced flexural rigidity so as to be easily deflected. In the status that the bumps are joined to corresponding circuitry electrodes on the substrate, the semiconductor element can deflect at other portions other than its surface between two adjacent bumps according to contraction and distortion of the substrate. This allows the bumps to be dislocated in a direction parallel to a surface of the semiconductor element, hence relieving stress developed by the contraction of the substrate at the joint positions between the bumps and the circuitry electrodes.Type: GrantFiled: December 12, 2001Date of Patent: September 9, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tadahiko Sakai, Mitsuru Ozono, Shoji Sakemi, Yoshiyuki Wada
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Patent number: 6536105Abstract: A conductive ball mounting equipment for mounting conductive balls on electrodes of a plurality of electronic components formed on a substrate, including a suction tool having a suction face to cover each one of divided blocks on the substrate, a suction part which is formed on the suction face of the suction tool, corresponding to the arrangement pitches of the electronic components and sucks the conductive balls to the positions corresponding to the electrodes, and a suction limiter for sucking the conductive balls only to the specified suction part corresponding to the electronic components in the divided blocks. According to this construction, the conductive balls can be efficiently and stably mounted on the electrodes of the electronic components of the substrate.Type: GrantFiled: March 15, 2000Date of Patent: March 25, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tadahiko Sakai, Shoji Sakemi, Kazuhiro Noda
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Publication number: 20020197877Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion 18a formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member 17 for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion 18b formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.Type: ApplicationFiled: June 21, 2002Publication date: December 26, 2002Applicant: Matsushita Electric Industrial Co. Ltd.Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi
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Electrode member for plasma treating apparatus, plasma treating apparatus and plasma treating method
Publication number: 20020195202Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.Type: ApplicationFiled: June 21, 2002Publication date: December 26, 2002Applicant: Matsushita Electric Industrial Co., LTDInventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi, Taiji Matano, Nobuhiro Satou -
Patent number: 6468582Abstract: The solder pre-coating method including cleaning by dry etching a surface of a gold film on a surface of an electrode formed on a circuit board by covering the surface of the circuit board with a template having an opening; adding tackiness on the surface of the electrode after cleaning by making a tackiness adding compound react with the electrode surface; attaching solder powder on the tackiness added electrode surface; and forming a solder pre-coat layer on the electrode surface by melting the solder powder by heating. Another solder pre-coating method of the present invention adds tackiness on a surface of a gold film on a surface of an electrode after forming a metal film containing one of copper or nickel on the surface of the gold film. According to the present invention, as it eliminates the need for masking work on each individual circuit board in pre-coating solder, a partially solder pre-coated circuit board can be obtained simply and at allow cost.Type: GrantFiled: April 4, 2000Date of Patent: October 22, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Shoji Sakemi
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Publication number: 20020148810Abstract: A surface treatment method for thinning a silicon based substrate obtains a milky-dull color on an overall surface uniformly of the silicon based substrate. To be more specific, a surface opposite to a circuit-formed surface is mechanically polished, then the surface is etched using inert gas such as argon gas for producing plasma. This etching forms micro dimples uniformly on the surface. Next, the surface is further etched using fluorine based gas for producing plasma. This etching obtains a milky-dull color uniformly on the surface. As a result, printed marks on the surface can be read with ease, and pick-up errors in die-bonding can be reduced.Type: ApplicationFiled: April 3, 2002Publication date: October 17, 2002Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi
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Publication number: 20020090826Abstract: A method of plasma processing a silicon-containing object to be processed at a high etching rate without causing a surface of the object to have a hazy appearance, so that this surface can have an excellent visual quality. In the plasma processing method of etching the surface of the semiconductor wafer, gas containing sulfur hexafluoride and helium is used as a plasma-generating gas. A fluorine radical as an active substance which reacts with silicon of the surface of the semiconductor wafer, gaseous silicon tetrafluoride yielded by the reaction and a compound (SFn) of fluorine and sulfur that is generated as a reaction product are removed by the helium gas functioning as carrier gas. The helium gas prevents the reaction product from adhering to the surface of the wafer again.Type: ApplicationFiled: January 7, 2002Publication date: July 11, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Shoji Sakemi
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Publication number: 20020084470Abstract: A semiconductor device assembly and a semiconductor device are provided which both can ensure reliability after a mounting process. The semiconductor device includes a semiconductor element equipped with bumps on an electrode patterned surface thereof for external connection. In the semiconductor device mounted on a substrate in the semiconductor device assembly, a semiconductor element shaped to have a thickness ranging 200 &mgr;m to 10 &mgr;m has reduced flexural rigidity so as to be easily deflected. In the status that the bumps are joined to corresponding circuitry electrodes on the substrate, the semiconductor element can deflect at other portion than its surface between two adjacent bumps according to contraction and distortion of the substrate. This allows the bumps to be dislocated in a parallel direction with a surface of the semiconductor element, hence relieving a stress developed by the contraction of the substrate at the joint positions between the bumps and the circuitry electrodes.Type: ApplicationFiled: December 12, 2001Publication date: July 4, 2002Inventors: Tadahiko Sakai, Mitsuru Ozono, Shoji Sakemi, Yoshiyuki Wada
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Publication number: 20020061642Abstract: The method of manufacturing a semiconductor device of the present invention includes steps of; a resin layer forming process in which a face with electrodes of a semiconductor wafer having a plurality of semiconductor elements formed thereon is coated with a resin layer which has a function of sealing it; and a wafer thinning process in which the back face of the semiconductor wafer is ground. The method of manufacturing the semiconductor device of the present invention further includes a process of forming a conductive section on the electrodes of the semiconductor wafer with a plurality of semiconductor elements in such a manner the conductive section reaches to the electrodes. The manufacturing method of the semiconductor device of the present invention still further includes a process of cutting the semiconductor wafer having a plurality of semiconductor elements along boundaries of each semiconductor element.Type: ApplicationFiled: January 11, 2002Publication date: May 23, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Haji, Shoji Sakemi
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Patent number: 6350664Abstract: The method of manufacturing a semiconductor device of the present invention includes steps of; a resin layer forming process in which a face with electrodes of a semiconductor wafer having a plurality of semiconductor elements formed thereon is coated with a resin layer which has a function of sealing it; and a wafer thinning process in which the back face of the semiconductor wafer is ground. The method of manufacturing the semiconductor device of the present invention further includes a process of forming a conductive section on the electrodes of the semiconductor wafer with a plurality of semiconductor elements in such a manner the conductive section reaches to the electrodes. The manufacturing method of the semiconductor device of the present invention still further includes a process of cutting the semiconductor wafer having a plurality of semiconductor elements along boundaries of each semiconductor element.Type: GrantFiled: August 25, 2000Date of Patent: February 26, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Haji, Shoji Sakemi
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Publication number: 20010018233Abstract: The method of manufacturing a semiconductor device of the present invention comprises: forming a resin layer on a surface of a semiconductor wafer on which a plurality of semiconductor elements are formed, forming through-holes on the resin layer, a first cutting of either the semiconductor wafer or the resin layer, mounting conductive balls on the through-hole, connecting the conductive ball to electrodes of the semiconductor element, and a second cutting for dividing the wafer into each piece of semiconductor devices. With the processes of the present invention, conductive balls can be easily and effectively mounted on a wafer under optimum conditions, without failure such as slipping or falling down from the required position. This fact contributes to an increased efficiency and a good productivity in the production of semiconductor devices.Type: ApplicationFiled: February 13, 2001Publication date: August 30, 2001Inventors: Hiroshi Haji, Shoji Sakemi, Mitsuru Ozono, Tadahiko Sakai, Kiyoshi Arita
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Patent number: 6179198Abstract: A method of soldering a bumped work without using flux is provided by the steps of vacuum-sucking the bumped work on a head, pressing a bump against a pad of another work, causing a projection of the bump to partially break an oxide film on the solder portion, to pierce it, and to be placed thereon, and cooling and solidifying the molten solder portion. The surface of the solder portion is coated by the oxide film as a hard shell, so that, even if the bump is firmly pressed against the solder portion, the solder of the solder portion does not flow sidewise, and a solder bridge is not produced.Type: GrantFiled: September 11, 1997Date of Patent: January 30, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideki Eifuku, Mitsuru Ozono, Tadahiko Sakai, Shoji Sakemi