Patents by Inventor Shoji Seta
Shoji Seta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230204769Abstract: Accurate information is acquired even in a case where a sensor is deteriorated. A ranging device according to an embodiment includes: a sensor (11) that acquires ranging information; a field-programmable gate array (FPGA) (131) that executes predetermined processing on the ranging information acquired by the sensor; and a memory (15) that stores data for causing the FPGA to execute the predetermined processing.Type: ApplicationFiled: May 28, 2021Publication date: June 29, 2023Inventor: SHOJI SETA
-
Patent number: 11457143Abstract: A sensor device according to an embodiment obtains accurate information even when there is deterioration in the sensor. The sensor device includes a sensor (11) that obtains sensor information; an FPGA (Field-Programmable Gate Array) (12) that performs predetermined processing on the sensor information obtained by the sensor; and a memory (15) that is used to store data, which is to be used in making the FPGA perform the predetermined processing.Type: GrantFiled: October 23, 2019Date of Patent: September 27, 2022Assignee: Sony Semiconductor Solutions CorporationInventor: Shoji Seta
-
Publication number: 20220291344Abstract: Safety of a user or the like is secured even when such malfunctions as a case that an optical system member has gone out of place occur. Provided is a protection cover which covers a light source device including a light source, an emitting section which is an optical system member that converts light of the light source into diffused light to emit the light, and a light receiving section that senses the light of the light source reflected by the emitting section. The protection cover which covers the light source device includes an opening arranged adjacent to the emitting section and having a shape that allows transmission of the emitted light and also that prevents a finger of a person from contacting the emitting section.Type: ApplicationFiled: June 4, 2020Publication date: September 15, 2022Inventors: TAKAHIRO WAKABAYASHI, SHOJI SETA
-
Publication number: 20200351440Abstract: A sensor device according to an embodiment obtains accurate information even when there is deterioration in the sensor. The sensor device includes a sensor (11) that obtains sensor information; an FPGA (Field-Programmable Gate Array) (12) that performs predetermined processing on the sensor information obtained by the sensor; and a memory (15) that is used to store data, which is to be used in making the FPGA perform the predetermined processing.Type: ApplicationFiled: October 23, 2019Publication date: November 5, 2020Inventor: Shoji Seta
-
Publication number: 20160344985Abstract: Solid-state imaging devices of embodiments include: a photoelectric conversion element, a first insulating layer and a microlens. The first insulting layer is formed on the photoelectric conversion element. The microlens is formed on the first insulating layer. At least one of the microlens and the first insulating layer includes material to be provided with a band-pass function of causing infrared light of a predetermined wavelength region to pass through.Type: ApplicationFiled: December 18, 2015Publication date: November 24, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Shoji SETA, Yojiro HAMASAKI
-
Patent number: 9191637Abstract: A solid-state imaging device according to an embodiment is a solid-state imaging device in which a plurality of pixel regions are formed into a two-dimensional array isolating the pixel regions from each other by element isolation regions, including a plurality of microlenses, a plurality of color filters arranged below the plurality of microlenses, a plurality of photoelectrical conversion sections arranged below the plurality of color filters and a magnetic field generating section provided on the element isolation regions between the plurality of microlenses and the plurality of photoelectrical conversion sections.Type: GrantFiled: February 20, 2014Date of Patent: November 17, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Shoji Seta
-
Publication number: 20150256770Abstract: A solid-state image sensor device according to an embodiment includes an image pickup section, a first read signal line, a second read signal line, and an exposure time control section. The image pickup section includes a plurality of pixels arranged two-dimensionally in a matrix form. The first read signal line controls reading of charge accumulated in the plurality of pixels and be connected to a first pixel arranged in a center of a first row on which the plurality of pixels are arranged. The second read signal line controls reading of charge accumulated in the plurality of pixels and be connected to a second pixel arranged in a periphery outside the center of the first row. The exposure time control section performs control so that an exposure time of the second pixel becomes longer than an exposure time of the first pixel.Type: ApplicationFiled: September 3, 2014Publication date: September 10, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Shoji SETA, Fumio Izawa
-
Publication number: 20150215527Abstract: According to an embodiment, a CPU of a smartphone executes: a first process for judging whether or not there is a first input corresponding to first registered information in a short-distance photographing mode; a second process for, when it is judged in the first process that the first input corresponding to the first registered information exists, performing image pickup by an image sensor after elapse of a first time period and displaying a still image picked up and obtained on the display device; a third process for judging whether or not there is a second input corresponding to second registered information after displaying the still image picked up and obtained by the second process on the display device; and a fourth process for recording the still image to a memory when it is judged in the third process that the second input corresponding to the second registered information exists.Type: ApplicationFiled: September 11, 2014Publication date: July 30, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Shoji SETA, Yoshihiko Tokito
-
Patent number: 9041134Abstract: A solid-state imaging device includes a pixel chip, a logic chip and one or more shielding layers. The one or more shielding layers are arranged between or within the pixel chip and/or the logic chip to shield or reduce the effect of electromagnetic interference, radiation generated noise, or electromagnetic waves generated in one portion of the solid-state imaging device from affecting another portion of the solid-state imaging device.Type: GrantFiled: August 30, 2013Date of Patent: May 26, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Shoji Seta
-
Publication number: 20150070538Abstract: A solid-state imaging device according to an embodiment is a solid-state imaging device in which a plurality of pixel regions are formed into a two-dimensional array isolating the pixel regions from each other by element isolation regions, including a plurality of microlenses, a plurality of color filters arranged below the plurality of microlenses, a plurality of photoelectrical conversion sections arranged below the plurality of color filters and a magnetic field generating section provided on the element isolation regions between the plurality of microlenses and the plurality of photoelectrical conversion sections.Type: ApplicationFiled: February 20, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Shoji Seta
-
Patent number: 8878371Abstract: A semiconductor device has a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof and has an approximately rectangular shape; a rewiring layer which is provided with a plurality of contact wiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film, and has an approximately rectangular shape; and a plurality of ball electrodes which are provided on the rewiring layer.Type: GrantFiled: April 17, 2013Date of Patent: November 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Seta, Hideaki Ikuma
-
Publication number: 20140284745Abstract: A solid-state imaging device includes a pixel chip, a logic chip and one or more shielding layers. The one or more shielding layers are arranged between or within the pixel chip and/or the logic chip to shield or reduce the effect of electromagnetic interference, radiation generated noise, or electromagnetic waves generated in one portion of the solid-state imaging device from affecting another portion of the solid-state imaging device.Type: ApplicationFiled: August 30, 2013Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Shoji SETA
-
Publication number: 20140071567Abstract: A semiconductor device according to an embodiment includes a plurality of pads, a plurality of ESD protection circuits, each one of the ESD protection circuits being connected to a corresponding one of the plurality of pads, and an I/O circuit which is connected to a connection portion connecting output terminals of the plurality of ESD protection circuits to each other and which receives at least one input signal inputted into the plurality of pads.Type: ApplicationFiled: February 28, 2013Publication date: March 13, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Shoji SETA
-
Patent number: 8653629Abstract: A semiconductor device has a semiconductor substrate. The semiconductor device has a plurality of LSI regions that are formed on the semiconductor substrate and are provided with a first power supply wiring layer including a first power supply wire. The semiconductor device has a first power supply terminal formed on the semiconductor substrate. The semiconductor device has a second power supply wiring layer including a second power supply wire that electrically connects the first power supply wire and the first power supply terminal, the second power supply wiring layer is formed in a dicing region between the LSI regions along a dicing line that separates the LSI regions and the dicing line region. A first barrier metal film is formed at least in the LSI regions at a boundary between the first power supply wire and the second power supply wire.Type: GrantFiled: September 19, 2011Date of Patent: February 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Seta, Yojiro Hamasaki
-
Publication number: 20130256886Abstract: A semiconductor device has a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof and has an approximately rectangular shape; a rewiring layer which is provided with a plurality of contact wiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film, and has an approximately rectangular shape; and a plurality of ball electrodes which are provided on the rewiring layer.Type: ApplicationFiled: April 17, 2013Publication date: October 3, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Shoji Seta, Hideaki Ikuma
-
Patent number: 8450855Abstract: A semiconductor device has a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof and has an approximately rectangular shape; a rewiring layer which is provided with a plurality of contact wiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film, and has an approximately rectangular shape; and a plurality of ball electrodes which are provided on the rewiring layer.Type: GrantFiled: March 14, 2011Date of Patent: May 28, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Seta, Hideaki Ikuma
-
Publication number: 20120242402Abstract: A semiconductor device has a semiconductor substrate. The semiconductor device has a plurality of LSI regions that are formed on the semiconductor substrate and are provided with a first power supply wiring layer including a first power supply wire. The semiconductor device has a first power supply terminal formed on the semiconductor substrate. The semiconductor device has a second power supply wiring layer including a second power supply wire that electrically connects the first power supply wire and the first power supply terminal, the second power supply wiring layer is formed in a dicing region between the LSI regions along a dicing line that separates the LSI regions and the dicing line region. A first barrier metal film is formed at least in the LSI regions at a boundary between the first power supply wire and the second power supply wire.Type: ApplicationFiled: September 19, 2011Publication date: September 27, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Shoji Seta, Yojiro Hamasaki
-
Patent number: 8269346Abstract: A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.Type: GrantFiled: March 14, 2011Date of Patent: September 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Shoji Seta, Hideaki Ikuma, Yukihito Oowaki
-
Publication number: 20120025377Abstract: A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.Type: ApplicationFiled: March 14, 2011Publication date: February 2, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Shoji Seta, Hideaki Ikuma, Yukihito Oowaki
-
Publication number: 20110298127Abstract: A semiconductor device has a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof and has an approximately rectangular shape; a rewiring layer which is provided with a plurality of contact wiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film, and has an approximately rectangular shape; and a plurality of ball electrodes which are provided on the rewiring layer.Type: ApplicationFiled: March 14, 2011Publication date: December 8, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Shoji Seta, Hideaki Ikuma