Patents by Inventor Shoji Yabe
Shoji Yabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150183925Abstract: A solid electrolytic capacitor is obtained by a method comprising dissolving a polymerizable material for being converted into a conductive polymer in a water-soluble organic solvent to obtain a solution, adding the solution to water while homogenizing the solution to obtain a sol, immersing an anode body having a dielectric layer in the surface of the anode body in the sol, and applying voltage using the anode body as a positive electrode and a counter electrode as a negative electrode placed in the sol to electropolymerize the polymerizable material. An electropolymerizable liquid for producing a conductive polymer, the liquid composed of a sol comprising water, a water-soluble organic solvent, and a polymerizable material for being converted into the conductive polymer.Type: ApplicationFiled: July 25, 2013Publication date: July 2, 2015Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Publication number: 20150162136Abstract: The present invention provides an anode body for capacitors, which is formed of a sintered body that is obtained by sintering a powder mixture of a tungsten powder and a tungsten trioxide powder, and wherein the ratio of the tungsten trioxide powder to the total amount of the tungsten powder and the tungsten trioxide powder is 1 to 13 mass %. The present invention is able to reduce the number of semiconductor layer formation wherein polymerization of a semiconductor precursor is carried out a plurality of times on a dielectric layer. Consequently, a solid electrolytic capacitor element, in which a semiconductor layer that is composed of a conductive polymer is formed on a dielectric layer that is formed on the outer surface layer and the inner surface layer of the fine pores of a tungsten sintered body, can be produced efficiently.Type: ApplicationFiled: May 17, 2013Publication date: June 11, 2015Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Publication number: 20140315039Abstract: A method for finely powdering tungsten powder, which includes dispersing tungsten powder in an aqueous solution containing an oxidizing agent to form an oxide film in the surface of the tungsten powder and removing the oxide film with an alkaline aqueous solution. Also disclosed is a method for producing fine tungsten powder, which includes obtaining tungsten powder having an average particle size of 0.05 to 0.5 ?m by a process including the above method for finely powdering. Also disclosed is a tungsten powder having an average particle size of 0.05 to 0.5 ?m, in which the dMS value (product of an average particle size d (?m), true density M (g/cm3) and BET specific surface area S (m2/g)) is within the range of 6±0.8.Type: ApplicationFiled: August 29, 2012Publication date: October 23, 2014Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Publication number: 20140294663Abstract: A method for finely powdering tungsten powder, which includes electrolytically oxidizing tungsten powder while stirring in an aqueous mineral-acid solution to form an oxide film in the surface of the tungsten powder and removing the oxide film with an alkaline aqueous solution; a method for producing tungsten powder to obtain fine tungsten powder by a process including the above method for finely powdering; and a tungsten powder having an average particle size of 0.04 to 0.4 ?m, in which the dMS value (product of an average particle size d (?m), true density M (g/cm3) and BET specific surface area S (m2/g)) is within the range of 6±0.4.Type: ApplicationFiled: August 29, 2012Publication date: October 2, 2014Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Publication number: 20140233154Abstract: A method of manufacturing an anode body of a capacitor. An anode body of a capacitor is obtained by sintering a molded body of tungsten powder, which includes sintering the molded body by exposing the molded body to silicon vapor so that at least a part of the surface of the obtained sintered body is made to be tungsten silicide.Type: ApplicationFiled: August 29, 2012Publication date: August 21, 2014Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Patent number: 7842103Abstract: The present invention relates to a production method of a solid electrolytic capacitor element wherein a semiconductor layer is formed by electrolytic polymerization on an oxide dielectric film formed on the surface of an electric conductor and an electrode layer is laminated thereon, comprising passing current providing a period for temporarily applying a reverse voltage during the electrolytic polymerization passing current using an electric conductor having a dielectric layer formed thereon as an anode and a negative electrode plate placed in the electrolyte as a cathode; a solid electrolytic capacitor element produced by the method; a solid electrolytic capacitor obtained from the solid electrolytic capacitor element and use thereof. According to the present invention, a solid electrolytic capacitor element in which a high quality semiconductor layer is formed in a short time can be produced, which enables to produce a solid electrolytic capacitor having a good ESR property.Type: GrantFiled: June 30, 2006Date of Patent: November 30, 2010Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Jig for producing capacitors, apparatus for producing capacitors and method for producing capacitors
Patent number: 7837185Abstract: The invention provides (1) a jig for producing capacitors, which stabilizes multiple long plates in order to simultaneously form dielectric layers on a plurality of conductors connected to the long plates and subsequently simultaneously form semiconductor layers thereon, wherein two edge-receiving portions to receive and fix the edges of each plate are electrically insulated from each other, (2) an apparatus comprising the jig for producing capacitors, having feeding terminals for forming dielectric layer and for forming semiconductor layer and long plates comprising a mechanism connecting multiple conductors, and a method for producing capacitors. According to the invention, capacitors each having semiconductor layer as one electrode, narrow in variation of capacitance, and excellent in the ESR value, can be produced at a time.Type: GrantFiled: November 2, 2005Date of Patent: November 23, 2010Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Shoji Yabe -
Patent number: 7811338Abstract: The invention produces a solid electrolytic capacitor using a solid electrolytic capacitor element by a method comprising forming a dielectric layer on the surface of an electric conductor, forming a semiconductor layer containing electrically conducting polymer on the dielectric layer and forming an electrode layer thereon, wherein the dielectric layer is formed by chemical formation in an electrolytic solution containing a dopant.Type: GrantFiled: March 29, 2006Date of Patent: October 12, 2010Assignee: Murata Manufacturing Co., Ltd.Inventors: Kazumi Naito, Shoji Yabe
-
Publication number: 20090225497Abstract: The present invention relates to a production method of a solid electrolytic capacitor element wherein a semiconductor layer is formed by electrolytic polymerization on an oxide dielectric film formed on the surface of an electric conductor and an electrode layer is laminated thereon, comprising passing current providing a period for temporarily applying a reverse voltage during the electrolytic polymerization passing current using an electric conductor having a dielectric layer formed thereon as an anode and a negative electrode plate placed in the electrolyte as a cathode; a solid electrolytic capacitor element produced by the method; a solid electrolytic capacitor obtained from the solid electrolytic capacitor element and use thereof. According to the present invention, a solid electrolytic capacitor element in which a high quality semiconductor layer is formed in a short time can be produced, which enables to produce a solid electrolytic capacitor having a good ESR property.Type: ApplicationFiled: June 30, 2006Publication date: September 10, 2009Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Publication number: 20080250621Abstract: The invention produces a solid electrolytic capacitor using a solid electrolytic capacitor element by a method comprising forming a dielectric layer on the surface of an electric conductor, forming a semiconductor layer containing electrically conducting polymer on the dielectric layer and forming an electrode layer thereon, wherein the dielectric layer is formed by chemical formation in an electrolytic solution containing a dopant.Type: ApplicationFiled: March 29, 2006Publication date: October 16, 2008Applicant: Showa Denko K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Jig For Producing Capacitors, Apparatus For Producing Capacitors And Method For Producing Capacitors
Publication number: 20080137261Abstract: The invention provides (1) a jig for producing capacitors, which stabilizes multiple long plates in order to simultaneously form dielectric layers on a plurality of conductors connected to the long plates and subsequently simultaneously form semiconductor layers thereon, wherein two edge-receiving portions to receive and fix the edges of each plate are electrically insulated from each other, (2) an apparatus comprising the jig for producing capacitors, having feeding terminals for forming dielectric layer and for forming semiconductor layer and long plates comprising a mechanism connecting multiple conductors, and a method for producing capacitors. According to the invention, capacitors each having semiconductor layer as one electrode, narrow in variation of capacitance, and excellent in the ESR value, can be produced at a time.Type: ApplicationFiled: November 2, 2005Publication date: June 12, 2008Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Shoji Yabe -
Publication number: 20080019080Abstract: The present invention relates to a method for producing a solid electrolytic capacitor element, comprising forming a dielectric layer by chemical formation on the surface of an electric conductor, and sequentially forming a semiconductor layer containing an electrically conducting polymer and an electrode layer on the dielectric layer, wherein after forming the semi-conductor layer, re-chemical formation is performed in an electrolytic solution using a dopant as the electrolyte to repair the dielectric layer after formation of the semiconductor layer. By using the solid electrolytic capacitor element of the present invention, a high-capacitance solid electrolytic capacitor with a good ESR value can be produced.Type: ApplicationFiled: September 12, 2005Publication date: January 24, 2008Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Patent number: 7291537Abstract: The invention provides a method for producing a solid electrolytic capacitor reliable with good LC value after mounting, wherein a solid electrolytic capacitor element comprises an anode body composed of a material containing at least one selected from a group consisting of an earth-acid metal, an alloy comprising an earth-acid metal as the main component, an electrically conducting oxide of an earth-acid metal and a mixture of two or more thereof, a dielectric layer formed on the anode body by electrolytic oxidation (electrochemical formation) and comprising an oxide as the main component, a semiconductor layer formed on the dielectric layer, and an electrically conducting layer stacked on the semiconductor layer, and the solid electrolytic capacitor element is molded with a resin, cured and then applied voltage (aging) treatment, which method comprises sequentially repeating a step of leaving the resin-molded body to stand at 225 to 305° C.Type: GrantFiled: July 16, 2004Date of Patent: November 6, 2007Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Publication number: 20070026622Abstract: The invention provides a method for producing a solid electrolytic capacitor reliable with good LC value after mounting, wherein a solid electrolytic capacitor element comprises an anode body composed of a material containing at least one selected from a group consisting of an earth-acid metal, an alloy comprising an earth-acid metal as the main component, an electrically conducting oxide of an earth-acid metal and a mixture of two or more thereof, a dielectric layer formed on the anode body by electrolytic oxidation (electrochemical formation) and comprising an oxide as the main component, a semiconductor layer formed on the dielectric layer, and an electrically conducting layer stacked on the semiconductor layer, and the solid electrolytic capacitor element is molded with a resin, cured and then applied voltage (aging) treatment, which method comprises sequentially repeating a step of leaving the resin-molded body to stand at 225 to 305° C.Type: ApplicationFiled: July 16, 2004Publication date: February 1, 2007Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Patent number: 7122063Abstract: A method for producing a capacitor which includes, as one electrode, an electrical conductor having formed on the surface thereof a dielectric layer and, as the other electrode, a semiconductor layer, the method including producing fine electrically defective portions in the dielectric layer and forming the semiconductor layer on the dielectric layer by electrification. The capacitor obtained by the method of the present invention has good capacitance appearance factor, low ESR and is excellent in reliability.Type: GrantFiled: February 6, 2004Date of Patent: October 17, 2006Assignee: Showa Denko K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Publication number: 20040223291Abstract: A method for producing a capacitor comprising, as one electrode, an electrical conductor having formed on the surface thereof a dielectric layer and, as the other electrode, a semiconductor layer, the method comprising producing fine electrically defective portions in the dielectric layer and forming the semiconductor layer on the dielectric layer by electrification.Type: ApplicationFiled: February 6, 2004Publication date: November 11, 2004Applicant: SHOWA DENKO K.K.Inventors: Kazumi Naito, Shoji Yabe
-
Patent number: 5406498Abstract: A floor-planning system of the present invention prepares a block diagram showing blocks and the connection status among the blocks. The floor-planning system inputs a block diagram, estimates the block sizes, and estimates the aspect ratio range possible for the blocks. The system refers to the estimated block sizes and the estimated aspect ratios to specify the shapes and the arrangement of the blocks in the layout area. The system displays the block arrangement and the connection status among the blocks. The block layout is stored as layout data and utilized in feasibility judgment for a layout area on an LSI or a PCB.Type: GrantFiled: February 8, 1993Date of Patent: April 11, 1995Assignee: NEC CorporationInventor: Shoji Yabe
-
Patent number: 5212651Abstract: In a scan path generation system, flip-flops and logic elements of a logic circuit are placed on an X-Y plane according to logical connection data and original scan path data. Data describing a sequence in which the flip-flops are to be arranged for the benefit of the geometry of the logic circuit is prepared and stored in a sequence table. The flip-flops on the X-Y plane are rearranged according to the data stored in the sequence table. New scan path data is derived from the rearranged flip-flops and are substituted for the original scan path data to be used for connecting the flip-flops. Due to the rearrangement process, the flip-flops can be connected in a scan path with relatively short and straight path sections between successive flip-flops, minimizing the amount of channel space which is occupied by the scan path.Type: GrantFiled: March 12, 1990Date of Patent: May 18, 1993Assignee: NEC CorporationInventor: Shoji Yabe
-
Patent number: 5164907Abstract: A system and method for logic circuit design in which functional blocks are placed on a substantially plane area in compliance with logic connection information under a circuit constraint. Critical nets are first extracted from logic connection information and then, critical blocks connected to the critical nets are extracted from the logic connection information. The critical blocks are initially placed on the substantially plane area to provide an initial critical block placement result. The initial critical block placement result is iteratively improved until the circuit constraint is satisfied.Type: GrantFiled: February 14, 1990Date of Patent: November 17, 1992Assignee: NEC CorporationInventor: Shoji Yabe
-
Patent number: 4975854Abstract: A location method in a layout design improves the efficiency of wiring connections among elements. For each row of cell units, the number of cells in variable length blocks and the number of terminals in each block are identified. After counting the available empty cells, the number of empty cells required by each block is calculated based on the number of cells and terminals in the block. For ech row of cells the empty cells are distributed to the blocks. The blocks are then located accordingly on the base structure.Type: GrantFiled: May 22, 1987Date of Patent: December 4, 1990Assignee: NEC CorporationInventor: Shoji Yabe