Abstract: A block placement method and system for automatically placing a plurality of blocks on a substrate. A temporary groundwork design is established which does not contain a block placement inhibited area, such area being reserved from power lines. Initially, the blocks are placed upon the temporary groundwork design in a provisional groundwork design. An extended block is obtained upon inserting a block placement inhibited areas into the provisional groundwork design. Wiring is routed within the extended block on a placed substrate.

Abstract: Disclosed is a solid electrolytic capacitor having a roll-form capacitor element. The capacitor element has a coated structure comprising a valve metal positive electrode substrate having a dielectric oxide layer on the surface thereof, a semiconductor layer formed on the dielectric oxide layer and an electroconductive layer formed on the semiconductor layer.

Abstract: A master slice integrated circuit comprises a first linear cell array of logic gates and a second linear cell array of first and second groups of flip-flop cells and a clock distributor cell having a plurality of clock outputs. To deduce the size of flip-flop cells and clock propagation times, the flip-flops are formed of custom-made circuit configuration. A wire pattern region is arranged in parallel with the first and second liner cell arrays for interconnecting the logic gates to create cells having desired logic functions and connecting inputs and outputs of the logic function cells to data inputs and outputs of the flip-flop cells and for connecting the clock outputs of the clock distributor cell to the clock inputs of the flip-flop cells.