Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a conductive layer provided on the substrate; a stacked body provided on the conductive layer and including a plurality of electrode layers stacked to be separated from each other; a semiconductor pillar portion provided in the stacked body and extending in a stacking direction of the stacked body; an interconnect portion provided in the stacked body, extending in the stacking direction and a first direction crossing the stacking direction, and including a lower surface; a semiconductor portion provided in the conductive layer via an insulating film relative to the conductive layer, provided integrally with the semiconductor pillar portion; and an insulating portion. The semiconductor portion includes: a first portion; a second portion; and a third portion. The insulating portion is provided between the first portion and the second portion.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a plurality of electrode layers separately stacked; a first upper layer gate provided on the stacked body; an interlayer insulating layer provided on the first upper layer gate; an insulating part continuously provided from the first upper layer gate to the substrate and extending in a first direction parallel to a major surface of the substrate; a second upper layer gate; a semiconductor part; a charge storage film; and a semiconductor layer provided from an upper end of the semiconductor part to a portion of the semiconductor part reaching the second upper layer gate. The second upper layer gate is provided on the interlayer insulating layer and the insulating part, and extends on a first surface parallel to the major surface.

Abstract: A manufacturing method of a semiconductor device according to an embodiment includes forming element isolation regions and active areas on a surface of a semiconductor substrate. A plurality of gate electrodes are formed above the active areas. Recesses that recess below surfaces of the element isolation regions are formed in the active areas by selectively etching the active areas between the gate electrodes. An interlayer dielectric film is deposited on the active areas, the element isolation regions, and the gate electrodes. A contact holes are formed on the recesses by etching the interlayer dielectric film using anisotropic etching. A bottom of each contact holes is widened by further etching the interlayer dielectric film on an inner wall of each contact hole using isotropic etching. Contacts contacting the recesses in the active areas are formed by embedding a conductive material in the contact holes.