Patents by Inventor Shou-Wen Kuo
Shou-Wen Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961770Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: GrantFiled: November 4, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
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Patent number: 11929271Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing; a load port; a robot arm inside the housing; and a processor. The load port is configured to load a wafer carrier into the housing. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.Type: GrantFiled: July 13, 2020Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Kang Hu, Shou-Wen Kuo, Sheng-Hsiang Chuang, Jiun-Rong Pai, Hsu-Shui Liu
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Patent number: 11842481Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.Type: GrantFiled: August 4, 2022Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Publication number: 20230386887Abstract: A system and method for cleaning ring frames is disclosed. In one embodiment, a ring frame processing system includes: a plurality of blades for mechanically removing tapes and tape residues from surfaces of a ring frame; a plurality of wheel brushes for conditioning the surfaces of the ring frame; and a transport mechanism for transporting the ring frame.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Jian-Hung Cheng, M.C. Lin, C.C. Chien, Hsuan Lee, Boris Huang
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Patent number: 11764097Abstract: A system and method for cleaning and inspecting ring frames is disclosed here. In one embodiment, a ring frame processing system includes: a cleaning station configured to remove a first tape on a first surface of a ring frame using a first blade, clean first adhesive residues from the first tape on the first surface of the ring frame using a first wheel brush, and remove second adhesive residues from a second tape on a second surface of the ring frame using a second blade; and an inspection station, wherein the inspection station comprises an automated optical inspection system configured to determine the cleanness of the first and second surfaces of the ring frame after cleaning.Type: GrantFiled: May 5, 2021Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Jian-Hung Cheng, M. C. Lin, C. C. Chien, Hsuan Lee, Boris Huang
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Patent number: 11754989Abstract: A semiconductor equipment management method applicable to an electronic device for managing multiple pieces of semiconductor equipment is provided. The pieces of semiconductor equipment are respectively controlled through multiple control hosts, and the control hosts and the electronic device are connected to a switch device. The method includes: receiving real-time image information of each control host through the switch device; determining whether the real-time image information of each control host includes a triggering event by performing an image recognition on the real-time image information; executing a macro corresponding to the triggering event, where the macro includes at least one self-defined operation; generating at least one input command according to the self-defined operation of the executed macro; and controlling the control hosts to execute the self-defined operation of the executed macro by transmitting the input command to the control hosts through the switch device.Type: GrantFiled: November 16, 2020Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sing-Tsung Li, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Shou-Wen Kuo, Chien-Ko Liao
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Publication number: 20230221645Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate While spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.Type: ApplicationFiled: February 27, 2023Publication date: July 13, 2023Inventors: Ming-Hsuan CHUANG, Po-Sheng LU, Shou-Wen KUO, Cheng-Yi HUANG, Chia-Hung CHU
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Patent number: 11699619Abstract: Some embodiments relate to a processing tool for processing a singulated semiconductor die. The tool includes an evaluation unit, a drying unit, and a die wipe station. The evaluation unit is configured to subject the singulated semiconductor die to a liquid to detect flaws in the singulated semiconductor die. The drying unit is configured to dry the liquid from a frontside of the singulated semiconductor die. The die wipe station includes an absorptive drying structure configured to absorb the liquid from a backside of the singulated semiconductor die after the drying unit has dried the liquid from the frontside of the singulated semiconductor die.Type: GrantFiled: April 21, 2021Date of Patent: July 11, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Sheng Kuo, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Yang-Ann Chu
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Patent number: 11651981Abstract: A system and method for defect detection in a hole array on a substrate is disclosed herein. In one embodiment, a method for defect detection in a hole array on a substrate, includes: scanning a substrate surface using at least one optical detector, generating at least one image of the substrate surface; and analyzing the at least one image to detect defects in the hole array on the substrate surface based on a set of predetermined criteria.Type: GrantFiled: August 18, 2020Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiao-Rou Liao, Sheng-Hsiang Chuang, Cheng-Kang Hu, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Patent number: 11592748Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.Type: GrantFiled: November 14, 2019Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hsuan Chuang, Po-Sheng Lu, Shou-Wen Kuo, Cheng-Yi Huang, Chia-Hung Chu
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Patent number: 11545382Abstract: The present disclosure, in some embodiments, relates to an integrated chip processing tool. The integrated chip processing tool includes a first transfer module and a second transfer module. The first transfer module has a first robotic arm disposed within a housing. The first transfer module is configured to receive a single and unitary first die tray configured to hold a plurality of integrated chip (IC) die and to concurrently transfer all of the plurality of IC die held by the single and unitary first die tray to a single and unitary die boat. The second transfer module has an additional robotic arm disposed within the housing and configured to concurrently transfer all of the plurality of IC die from the single and unitary die boat to a single and unitary second die tray.Type: GrantFiled: April 21, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Pin-Yi Hsin, Shou-Wen Kuo, Patrick Lin
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Publication number: 20220415699Abstract: Disclosed is a vacuum chuck and a method for securing a warped semiconductor substrate during a semiconductor manufacturing process so as to improve its flatness during a semiconductor manufacturing process. For example, a semiconductor manufacturing system includes: a vacuum chuck configured to hold a substrate, wherein the vacuum chuck comprises, a plurality of vacuum grooves located on a top surface of the vacuum chuck, wherein the top surface is configured to face the substrate; and a plurality of flexible seal rings disposed on the vacuum chuck and extending outwardly from the top surface, wherein the plurality of flexible seal rings are configured to directly contact a bottom surface of the substrate and in adjacent to the plurality of vacuum grooves so as to form a vacuum seal between the substrate and the vacuum chuck, and wherein each of the plurality of flexible seal rings has a zigzag cross section.Type: ApplicationFiled: August 8, 2022Publication date: December 29, 2022Inventors: Chien-Fa LEE, Chin-Lin CHOU, Shang-Ying TSAI, Shou-Wen KUO, Kuei-Sung CHANG, Jiun-Rong PAI, Hsu-Shui LIU, Chun-Wen CHENG
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Publication number: 20220375057Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.Type: ApplicationFiled: August 4, 2022Publication date: November 24, 2022Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Patent number: 11508608Abstract: Disclosed is a vacuum chuck and a method for securing a warped semiconductor substrate during a semiconductor manufacturing process so as to improve its flatness during a semiconductor manufacturing process. For example, a semiconductor manufacturing system includes: a vacuum chuck configured to hold a substrate, wherein the vacuum chuck comprises, a plurality of vacuum grooves located on a top surface of the vacuum chuck, wherein the top surface is configured to face the substrate; and a plurality of flexible seal rings disposed on the vacuum chuck and extending outwardly from the top surface, wherein the plurality of flexible seal rings are configured to directly contact a bottom surface of the substrate and in adjacent to the plurality of vacuum grooves so as to form a vacuum seal between the substrate and the vacuum chuck, and wherein each of the plurality of flexible seal rings has a zigzag cross section.Type: GrantFiled: August 20, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Fa Lee, Chin-Lin Chou, Shang-Ying Tsai, Shou-Wen Kuo, Kuei-Sung Chang, Jiun-Rong Pai, Hsu-Shui Liu, Chun-wen Cheng
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Publication number: 20220333246Abstract: A gas tube, a gas supply system containing the same and a semiconductor manufacturing method using the same are provided. The gas tube includes a porous material body and a resistant sheath surrounding the porous material body. The porous material body has a hollow tube structure and an empty cavity inside the hollow tube structure. The porous material body is hydrophobic and has a plurality of pores therein. The resistant sheath is disposed on the porous material body and surrounds the porous material body. The resistant sheath includes a plurality of holes penetrating through the resistant sheath.Type: ApplicationFiled: June 29, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Shiung Chen, Cheng-Yi Huang, Chih-Shen Yang, Shou-Wen Kuo, Po-Wen Chai
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Patent number: 11430108Abstract: A method includes: receiving a defect map from a defect scanner, wherein the defect map comprises at least one defect location of a semiconductor workpiece; annotating the defect map with a reference fiducial location of the semiconductor workpiece; determining a detected fiducial location within image data of the semiconductor workpiece; determining an offset correction based on comparing the detected fiducial location with the reference fiducial location; producing a corrected defect map by applying the offset correction to the defect map, wherein the applying the offset correction translocates the at least one defect location; and transferring the corrected defect map to a defect reviewer configured to perform root cause analysis based on the corrected defect map.Type: GrantFiled: November 16, 2020Date of Patent: August 30, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Ko Liao, Ya-Hsun Hsueh, Sheng-Hsiang Chuang, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Publication number: 20220261001Abstract: In an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.Type: ApplicationFiled: May 4, 2022Publication date: August 18, 2022Inventors: Cheng-Kang HU, Cheng-Hung CHEN, Yan-Han CHEN, Feng-Kuang WU, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO
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Patent number: 11414757Abstract: A gas tube, a gas supply system containing the same and a semiconductor manufacturing method using the same are provided. The gas tube includes a porous material body and a resistant sheath surrounding the porous material body. The porous material body has a hollow tube structure and an empty cavity inside the hollow tube structure. The porous material body is hydrophobic and has a plurality of pores therein. The resistant sheath is disposed on the porous material body and surrounds the porous material body. The resistant sheath includes a plurality of holes penetrating through the resistant sheath.Type: GrantFiled: October 28, 2018Date of Patent: August 16, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Shiung Chen, Cheng-Yi Huang, Chih-Shen Yang, Shou-Wen Kuo, Po-Wen Chai
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Patent number: 11334080Abstract: In an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.Type: GrantFiled: September 24, 2019Date of Patent: May 17, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Kang Hu, Cheng-Hung Chen, Yan-Han Chen, Feng-Kuang Wu, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Publication number: 20220059415Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu