Patents by Inventor Shoujun Wang
Shoujun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230286679Abstract: An offshore rocket transport and launch method includes S1: assembling a rocket horizontally; S2: loading the assembled rocket as a whole into a transport cage; S3: transporting, by a transport vehicle, the transport cage loaded with the rocket to a wharf by land horizontal transport; S4: transferring the transport cage loaded with the rocket to a transport ship, and transporting the transport cage loaded with the rocket to an offshore rocket launch pad by sea transport; S5: hoisting, by a hoisting device, the transport cage loaded with the rocket to the rocket launch pad; S6: opening the transport cage, transferring the rocket to a launching position, and hoisting the transport cage away from the rocket launch pad; and S7: launching the rocket. The method effectively facilitates the offshore rocket transport and launch process, and prevents the rocket from being affected by the external environment during the launch process.Type: ApplicationFiled: October 14, 2022Publication date: September 14, 2023Applicants: Ludong University, Land Sea Space (Yantai) Information Technology Co., Ltd.Inventors: Qingtao GONG, Yao TENG, Shoujun WANG, Haipeng WANG, Zhongyu SUN, Kechang SHEN, Tianhua JIANG, Lu LIU, Liyan JIN, You HE
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Patent number: 11732999Abstract: An erection device and method for the marine hot launch of a rocket are provided. The erection device includes a launch vessel, a launch pad, an erection assembly, a guide member, a driving cylinder, a sliding member, and a connecting member. The sliding member cooperates with the guide member and is driven by the driving cylinder to move linearly. The connecting member has one end hinged to the erection assembly at a certain angle and the other end connected to the sliding member and is configured to move with the sliding member to drive the erection assembly to be erected on the launch pad. The erection device and method can achieve an effective erection of the rocket for marine hot launch with a desired erection effect and high stability.Type: GrantFiled: December 2, 2021Date of Patent: August 22, 2023Assignee: Ludong UniversityInventors: Qingtao Gong, Yao Teng, Fuzhen Pang, Kangqiang Li, Haichao Li, Yuan Du, Shoujun Wang, Gang Wang, Kechang Shen, Shilong He, Liyan Jin
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Publication number: 20230213310Abstract: An erection device and method for the marine hot launch of a rocket are provided. The erection device includes a launch vessel, a launch pad, an erection assembly, a guide member, a driving cylinder, a sliding member, and a connecting member. The sliding member cooperates with the guide member and is driven by the driving cylinder to move linearly. The connecting member has one end hinged to the erection assembly at a certain angle and the other end connected to the sliding member and is configured to move with the sliding member to drive the erection assembly to be erected on the launch pad. The erection device and method can achieve an effective erection of the rocket for marine hot launch with a desired erection effect and high stability.Type: ApplicationFiled: December 2, 2021Publication date: July 6, 2023Applicant: Ludong UniversityInventors: Qingtao GONG, Yao TENG, Fuzhen PANG, Kangqiang LI, Haichao LI, Yuan DU, Shoujun WANG, Gang WANG, Kechang SHEN, Shilong HE, Liyan JIN
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Publication number: 20220297567Abstract: A power charge control method including acquiring a standard power range of a battery; sending the standard power range to a user terminal; receiving a power charge target value in the standard power range that is fed back by the user terminal according to the standard power range; and performing power charge control with respect to the battery according to the power charge target value.Type: ApplicationFiled: March 17, 2022Publication date: September 22, 2022Inventors: Yongbin Sun, Shoujun Wang, Yaxin Bao
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Patent number: 9077330Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: GrantFiled: September 10, 2013Date of Patent: July 7, 2015Assignee: Altera CorporationInventors: Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong H. Lee
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Publication number: 20140009188Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: ApplicationFiled: September 10, 2013Publication date: January 9, 2014Applicant: Altera CorporationInventors: Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong H. Lee
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Patent number: 8570197Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: GrantFiled: November 24, 2010Date of Patent: October 29, 2013Assignee: Altera CorporationInventors: Toan Thanh Nguyen, Thungoc Tran, Sergey Yuryevich Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong Lee
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Patent number: 8217693Abstract: Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.Type: GrantFiled: February 14, 2011Date of Patent: July 10, 2012Assignee: Altera CorporationInventors: Haitao Mei, Shoujun Wang, William Bereza, Tad Kwasniewski
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Patent number: 8115532Abstract: A method and circuit for generating an adjustable delay signal is presented, wherein the delay can be linear and monotonic with high resolution delay steps. The circuit utilizes one or more serially coupled delay cells and a load cell. Each delay cell comprises an inverter, a nor-multiplexer, and a programmable capacitor, wherein a first control signal is used to control the operation of the nor-multiplexer and a second control signal is used to control capacitance of the programmable capacitor. Values of the first and the second control signals are selected based on any desired range of total delay time and any desired delay time for a specific application of the circuit.Type: GrantFiled: July 11, 2008Date of Patent: February 14, 2012Assignee: Integrated Device Technology, Inc.Inventors: Shengyuan Zhang, Shoujun Wang, Yong Wang
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Publication number: 20110156806Abstract: Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.Type: ApplicationFiled: February 14, 2011Publication date: June 30, 2011Inventors: Haitao Mei, Shoujun Wang, William Bereza, Tad Kwasniewski
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Publication number: 20110068845Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: ApplicationFiled: November 24, 2010Publication date: March 24, 2011Inventors: Toan Thanh Nguyen, Thungoc Tran, Sergey Yuryevich Shumarayev, Arch ZaIiznyak, Shoujun Wang, Ramanand Venkata, Chong Lee
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Patent number: 7902888Abstract: Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.Type: GrantFiled: May 15, 2008Date of Patent: March 8, 2011Assignee: Altera CorporationInventors: Haitao Mei, Shoujun Wang, William Bereza, Tad Kwasniewski
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Patent number: 7848318Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: GrantFiled: February 27, 2006Date of Patent: December 7, 2010Assignee: Altera CorporationInventors: Toan Thanh Nguyen, Thungoc Tran, Sergey Yuryevich Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong Lee
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Patent number: 7848402Abstract: Methods and circuits are provided for producing phase-adjusted pre-emphasis and equalization. In applications in which little or no phase distortion occurs during signal transmission, propagation, or reception, linear-phase pre-emphasis or equalization can be used to reduce or eliminate phase distortion introduced by the pre-emphasis or equalization. Linear phase, constant group delay FIR filters or circuits may have odd numbers of coefficients symmetrical about the middle coefficient. In applications in which signal phase distortion occurs, linear phase or non-linear phase pre-emphasis or equalization can be used to reduce or compensate for the phase distortion. Phase compensation may be effected using FIR pre-emphasis and equalization filters and circuits. Non-linear phase FIR filters may have different numbers and combinations of coefficients.Type: GrantFiled: September 29, 2005Date of Patent: December 7, 2010Assignee: Altera CorporationInventors: Shoujun Wang, Yuming Tao, Tad Kwasniewski, William Bereza
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Patent number: 7839192Abstract: Duty cycle correction (DCC) methods and circuits are provided for improving the quality of clock signals and reducing or eliminating duty cycle distortion. The performance of known duty cycle correction circuits, such as cross-coupled inverter or transmission gate DCC circuits, may be improved by coupling two or more DCC circuits in series to form a multi-stage DCC circuit. In multi-stage DCC circuits, the performance and sizing requirements imposed on the individual circuit stages are reduced as compared to single-stage DCC circuit implementations. Good duty cycle correction performance over a wide range of input signal duty cycles may therefore be ensured regardless of the performance of individual stages. Clocked-CMOS DCC circuits are also presented, the circuits operative to produce duty cycle corrected output signals while consuming minimal current and power. The clocked-CMOS DCC circuits include as few as four transistors, and are operative over wide ranges of input signal duty cycles.Type: GrantFiled: October 26, 2005Date of Patent: November 23, 2010Assignee: Altera CorporationInventor: Shoujun Wang
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Patent number: 7750666Abstract: A reduced power differential type termination circuit for use in SSTL, HSTL and other transmission line systems reduces power consumption. A differential type termination circuit may comprise first and second nodes for coupling, respectively, to first and second transmission lines; a first impedance coupled between the first transmission line and a third node; a second impedance coupled between the second transmission line and the third node; and a low direct current reference voltage generator for generating a reference voltage applied to the third node. The first and second transmission lines may transmit complimentary signals. The first and second impedances may be symmetric or asymmetric. The first impedance may match the second impedance. The first and second impedances may, respectively, match the impedances of the first and second transmission lines. The first and/or second impedances may include a bidirectional switch, such as a transmission gate, to enable and disable the termination circuit.Type: GrantFiled: September 15, 2008Date of Patent: July 6, 2010Assignee: Integrated Device Technology, Inc.Inventors: Yu Min Zhang, Shoujun Wang
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Patent number: 7743288Abstract: A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (BIST) circuitry. The built-in, at-speed BERT provides a low-cost solution for production testing of high-speed serial links, facilitating jitter analysis and evaluation of pre-emphasis and equalization performance. This further allows adaptation of pre-emphasis and equalization.Type: GrantFiled: June 1, 2005Date of Patent: June 22, 2010Assignee: Altera CorporationInventor: Shoujun Wang
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Patent number: 7697603Abstract: Equalization circuitry that includes an analog equalizer and a decision feedback equalizer (DFE) is provided for high-speed backplane data communication. The analog equalizer reduces the number of taps that are required by the DFE, which lessens the error propagation of the DFE. Furthermore, the DFE includes a summing circuit and flip-flop circuitry. The flip-flop circuitry may be used as part of a phase detector by clock and data recovery circuitry. The summing circuit may further be embedded into the flip-flop circuitry to reduce the feedback path delay, thereby allowing for higher speed operation. The DFE may be extended to multiple taps by including additional flip-flops.Type: GrantFiled: October 18, 2004Date of Patent: April 13, 2010Assignee: Altera CorporationInventors: Shoujun Wang, Tad Kwasniewski, Bill Bereza
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Patent number: D1006681Type: GrantFiled: September 4, 2018Date of Patent: December 5, 2023Inventors: Bing Chang, Shoujun Wang, Juan Hao, Yongtao Zhang, Yuanchao Shi
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Patent number: D1013577Type: GrantFiled: May 9, 2018Date of Patent: February 6, 2024Assignee: BEIJING ELECTRIC VEHICLE CO., LTD.Inventors: Gaowa Wulin, Xiaokang Zhang, Heming Zhao, Liqing Zhu, Shoujun Wang