Abstract: Provided is a method for preparing a negative electrode sheet of nickel-metal hydride battery. The method includes steps of: obtaining a substrate roll; unwinding the substrate roll to unroll the substrate roll to form a substrate assembly (100), the substrate assembly (100) having a first-ring exposed segment (110), a middle-ring covered segment (120) and a tail-ring exposed segment (130) which are sequentially connected; and performing a slurry pulling treatment on the substrate assembly (100) to form a first active layer (210) and a second active layer (220) that are formed together on two opposite side faces of the substrate assembly (100), the first active layer (210) being attached to the first-ring exposed segment (110) and the middle-ring covered segment (120), and the second active layer (220) being attached to the middle-ring covered segment (120) and the tail-ring exposed segment (130).

Abstract: Provided is a method for preparing a negative electrode sheet of nickel-metal hydride battery. The method includes steps of: obtaining a substrate roll; unwinding the substrate roll to unroll the substrate roll to form a substrate assembly (100), the substrate assembly (100) having a first-ring exposed segment (110), a middle-ring covered segment (120) and a tail-ring exposed segment (130) which are sequentially connected; and performing a slurry pulling treatment on the substrate assembly (100) to form a first active layer (210) and a second active layer (220) that are formed together on two opposite side faces of the substrate assembly (100), the first active layer (210) being attached to the first-ring exposed segment (110) and the middle-ring covered segment (120), and the second active layer (220) being attached to the middle-ring covered segment (120) and the tail-ring exposed segment (130).

Abstract: An offshore rocket transport and launch method includes S1: assembling a rocket horizontally; S2: loading the assembled rocket as a whole into a transport cage; S3: transporting, by a transport vehicle, the transport cage loaded with the rocket to a wharf by land horizontal transport; S4: transferring the transport cage loaded with the rocket to a transport ship, and transporting the transport cage loaded with the rocket to an offshore rocket launch pad by sea transport; S5: hoisting, by a hoisting device, the transport cage loaded with the rocket to the rocket launch pad; S6: opening the transport cage, transferring the rocket to a launching position, and hoisting the transport cage away from the rocket launch pad; and S7: launching the rocket. The method effectively facilitates the offshore rocket transport and launch process, and prevents the rocket from being affected by the external environment during the launch process.

Abstract: An offshore rocket transport and launch method includes S1: assembling a rocket horizontally; S2: loading the assembled rocket as a whole into a transport cage; S3: transporting, by a transport vehicle, the transport cage loaded with the rocket to a wharf by land horizontal transport; S4: transferring the transport cage loaded with the rocket to a transport ship, and transporting the transport cage loaded with the rocket to an offshore rocket launch pad by sea transport; S5: hoisting, by a hoisting device, the transport cage loaded with the rocket to the rocket launch pad; S6: opening the transport cage, transferring the rocket to a launching position, and hoisting the transport cage away from the rocket launch pad; and S7: launching the rocket. The method effectively facilitates the offshore rocket transport and launch process, and prevents the rocket from being affected by the external environment during the launch process.

Abstract: An erection device and method for the marine hot launch of a rocket are provided. The erection device includes a launch vessel, a launch pad, an erection assembly, a guide member, a driving cylinder, a sliding member, and a connecting member. The sliding member cooperates with the guide member and is driven by the driving cylinder to move linearly. The connecting member has one end hinged to the erection assembly at a certain angle and the other end connected to the sliding member and is configured to move with the sliding member to drive the erection assembly to be erected on the launch pad. The erection device and method can achieve an effective erection of the rocket for marine hot launch with a desired erection effect and high stability.

Abstract: An erection device and method for the marine hot launch of a rocket are provided. The erection device includes a launch vessel, a launch pad, an erection assembly, a guide member, a driving cylinder, a sliding member, and a connecting member. The sliding member cooperates with the guide member and is driven by the driving cylinder to move linearly. The connecting member has one end hinged to the erection assembly at a certain angle and the other end connected to the sliding member and is configured to move with the sliding member to drive the erection assembly to be erected on the launch pad. The erection device and method can achieve an effective erection of the rocket for marine hot launch with a desired erection effect and high stability.

Abstract: A power charge control method including acquiring a standard power range of a battery; sending the standard power range to a user terminal; receiving a power charge target value in the standard power range that is fed back by the user terminal according to the standard power range; and performing power charge control with respect to the battery according to the power charge target value.

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.

Abstract: A method and circuit for generating an adjustable delay signal is presented, wherein the delay can be linear and monotonic with high resolution delay steps. The circuit utilizes one or more serially coupled delay cells and a load cell. Each delay cell comprises an inverter, a nor-multiplexer, and a programmable capacitor, wherein a first control signal is used to control the operation of the nor-multiplexer and a second control signal is used to control capacitance of the programmable capacitor. Values of the first and the second control signals are selected based on any desired range of total delay time and any desired delay time for a specific application of the circuit.

Abstract: Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: Methods and circuits are provided for producing phase-adjusted pre-emphasis and equalization. In applications in which little or no phase distortion occurs during signal transmission, propagation, or reception, linear-phase pre-emphasis or equalization can be used to reduce or eliminate phase distortion introduced by the pre-emphasis or equalization. Linear phase, constant group delay FIR filters or circuits may have odd numbers of coefficients symmetrical about the middle coefficient. In applications in which signal phase distortion occurs, linear phase or non-linear phase pre-emphasis or equalization can be used to reduce or compensate for the phase distortion. Phase compensation may be effected using FIR pre-emphasis and equalization filters and circuits. Non-linear phase FIR filters may have different numbers and combinations of coefficients.