Abstract: A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.

Abstract: Data transmitter circuitry on a programmable logic device (“PLD”) includes a plurality of channels of serializer circuitry, and a plurality of clock multiplier units (“CMUs”), each of which is associated with a respective subplurality of the serializer channels. Each CMU includes multiple reference clock signal sources, multiple phase-locked loop (“PLL”) circuits, and circuitry for allowing any PLL to get its reference input from any of the reference sources. Raw and centrally processed clock signals produced by each CMU are distributed to the serializer channels associated with that CMU and, at least in the case of the centrally processed signals, to the serializer channels associated with another CMU. The signal that controls release of parallel data to each serializer channel can be an output signal of that channel, or it can be an output signal of any CMU from which that channel can get a clock signal.

Abstract: Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.

Abstract: Possible deficiencies of a communication link are detected and automatically counteracted, at least to some degree. The deficiencies addressed can include phase shift and attenuation compensation. The counter-action can include adjustment of pre-emphasis given a signal applied to the communication link and/or adjustment of equalization given a signal received from the communication link.

Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.

Abstract: Voltage controlled oscillator (“VCO”) circuitry includes LC tank or ring VCO circuitry and frequency divider circuitry that divides the frequency output by the oscillator circuitry by a selectable integer factor that is at least 2 in the case of a ring oscillator or at least 4 in the case of an LC tank oscillator. This arrangement allows the oscillator circuitry to operate at frequencies that are higher than the desired final output frequencies, which has such advantages as reducing the size and power consumption of the oscillator circuitry, and allowing the circuitry as a whole to have a wide range of operating frequencies while reducing the frequency range over which the oscillator circuitry may be required to operate.

Abstract: Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract: Data transmitter circuitry on a programmable logic device (“PLD”) includes a plurality of channels of serializer circuitry, and a plurality of clock multiplier units (“CMUs”), each of which is associated with a respective subplurality of the serializer channels. Each CMU includes multiple reference clock signal sources, multiple phase-locked loop (“PLL”) circuits, and circuitry for allowing any PLL to get its reference input from any of the reference sources. Raw and centrally processed clock signals produced by each CMU are distributed to the serializer channels associated with that CMU and, at least in the case of the centrally processed signals, to the serializer channels associated with another CMU. The signal that controls release of parallel data to each serializer channel can be an output signal of that channel, or it can be an output signal of any CMU from which that channel can get a clock signal.

Abstract: A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector, a charge pump, an RC loop filter, and signal generator (e.g., a voltage controlled oscillator (VCO)). At low data rates, the loop may be operated with the charge pump and loop filter with stable second-order behavior, with the resistor R of the loop filter serving as a proportional path. A separate proportional path is also provided that provides phase detector output directly to a control input of the VCO, while the resistor R of the loop filter is also bypassed. As increasing data rates give rise to third-order effects, the separate proportional path may be activated to maintain second-order behavior.

Abstract: Circuitry and methods allow signal detection based entirely on differential voltage pairs. An incoming differential data signal is processed by separate full-wave rectifiers to extract high and low peak voltage envelopes. The rectifiers utilize negative feedback to ensure accurate envelope detection, and can detect peaks regardless of incoming signal polarity. The extracted envelopes are compared to a differential pair of threshold voltages. If the envelope signals have a smaller voltage difference than that of the threshold signals, the final output of the detector indicates that a loss-of-signal condition has occurred. Fully differential operation makes the detector independent of common-mode voltage, and thus more robust.

Abstract: A recovered clock signal is aligned (“eye centered”) with a data signal from which it is recovered by intentionally varying one of the factors or parameters that causes misalignment. For example, if a loop circuit (i.e., a phase-locked loop or a delay-locked loop) is used to recover the clock signal, charge pump current mismatch in the charge pump of the loop circuit is normally one factor in clock-data misalignment, and is also a parameter that can be manipulated. During a test mode, the current mismatch can be varied to obtain the best error rate, which signifies the best clock-data alignment. The test mode can be implemented using built-in self-test circuitry already on the device to transmit test data and then to receive it and analyze it for errors.

Abstract: An integrated circuit (IC) includes a ring oscillator. One may tune the ring oscillator by controlling a power supply of the ring oscillator. One may further tune ring oscillator by varying a capacitance of at least one varactor. Using the tuning techniques, one may tune the output frequency of the ring oscillator to a desired frequency.

Abstract: An integrated circuit (IC) includes a ring oscillator. One may tune the ring oscillator by controlling a power supply of the ring oscillator. One may further tune ring oscillator by varying a capacitance of at least one varactor. Using the tuning techniques, one may tune the output frequency of the ring oscillator to a desired frequency.

Abstract: A half-rate linear phase detector is particularly well-suited to clock data recovery in a serial data interface. The phase detector uses a quadrature clock to process different portions of the incoming data with different phases of the clock. The resulting component signals can be combined to provide the expected UP and DOWN phase detector output control signals. The phase detector output signals are balanced and of uniform width, minimizing oscillator control signal ripple in the clock data recovery circuit, while the linearity of the phase detector makes its output predictable.

Abstract: Pre-emphasis is given to differential output signals emanating from a pair of output nodes by initially (after an input data signal transition) connecting at least two current circuits to only one of the nodes. After a time delay, one of the current circuits is switched to connect only to the node to which the current circuits were not previously connected if there has been no further transition in the input data signal during the time delay. If only single-ended (i.e., non-differential) output is desired, only one of the output nodes is used as an output signal source. More than two current circuits may be used, and their switching from one node to the other may be performed progressively to provide pre-emphasis having any of many different characteristics.

Abstract: Systems and methods for correcting distortions in transmitted signals are provided. More particularly, systems and methods for correcting the asymmetry that may occur between a receiver's signal-eye and a distorted signal are provided. One technique centers the signal-eye, with respect to the received signal, by adjusting the voltage threshold of the signal-eye in the receiver's clock and data recovery decision circuit. Another technique centers the signal-eye, with respect to the received signal, by shaping the voltage of the received signal. A current-mode logic circuit is provided to shape the voltage of the received signal by sinking current from the received signal.

Abstract: Possible deficiencies of a communication link are detected and automatically counteracted, at least to some degree. The deficiencies addressed can include phase shift and attenuation compensation. The counter-action can include adjustment of pre-emphasis given a signal applied to the communication link and/or adjustment of equalization given a signal received from the communication link.

Abstract: Pre-emphasis is given to differential output signals emanating from a pair of output nodes by initially (after an input data signal transition) connecting at least two current circuits to only one of the nodes. After a time delay, one of the current circuits is switched to connect only to the node to which the current circuits were not previously connected if there has been no further transition in the input data signal during the time delay. If only single-ended (i.e., non-differential) output is desired, only one of the output nodes is used as an output signal source. More than two current circuits may be used, and their switching from one node to the other may be performed progressively to provide pre-emphasis having any of many different characteristics.

Abstract: A circuit and methods for use in increasing both bandwidth and switching speed of CML circuits. Two differential pairs are provided with one differential pair having a size that is a fraction of the other pair. Thus, one pair will have a size of W while the other will have a size of W/A. Each one of the first differential pair is coupled to at least one of the second pair. By reconfiguring the connections between the two pairs, circuits which have fast charging/discharging times and increased bandwidth are obtained.