Abstract: A semiconductor memory device including a memory cell group comprising a plurality of memory cells arranged in a matrix; a specification circuit for specifying a plurality of memory cells addressed by sequential addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number in response to cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles in response to the basic clock signal, and for instructing the counter circuit to count the number of cycles i

Abstract: According to this invention, in a data bit array for storing data, a plurality of memory cells capable of storing 4-level data are arranged in column and row directions. A check bit array for storing check data has a number of bits smaller than that of the data bit array. In the check bit array, a plurality of memory cells capable of storing 4-level data are arranged in column and row directions. A row address decoder selects one row from the check bit array and the data bit array in accordance with address data. Three sense amplifiers are connected to one column of the check bit array and the data bit array. The three sense amplifiers detect levels of data read from a memory cell in accordance with different reference levels in data read access, receive a plurality of precharge levels corresponding to 4-level write data, and write one of the precharged levels in the corresponding memory cell in accordance with write data.

Abstract: A semiconductor memory device has a memory cell array including many memory cells, a first data I/O section for implementing random input and output of data for the memory cells based on an externally-supplied random I/O signal, a second data I/O section for implementing serial input and output of data for the memory cells, a counter for counting the number of externally-supplied basic clock signal cycles, a controller for controlling the I/O of data for the memory cells in accordance with the number of the cycles of basic clock signals.

Abstract: A method for accessing a clock-synchronous semiconductor memory device including memory cells arranged in matrix. The cells are divided into at least two blocks, access to the cells in these blocks is designated from address data provided from an external device, and access to the memory cell is executed synchronously with an externally-supplied clock signal, which comprises setting the other blocks in an access preparation state or in an access operation standby state while one block is in an access operating state, setting a certain block in the access operating state via the access preparation state when the certain block is designated for the access operation by the address data and if the certain block is in the access operating state, and setting a certain block in the access operating state immediately when the certain block is designated for the access operation by the address data and if the certain block is in the access preparation state or in the access operation standby state.

Abstract: A semiconductor memory device including a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying a plurality of memory cells addressed by sequential addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number in response to cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles in response to the basic clock signal, and for instructing the counter circuit to count the number of cycles in

Abstract: A projection screen is comprised of a sheet formed by a multiplicity of light-transmitting plastic strands which strands are arranged and welded in parallel with one another. The width W (mm) of the screen and the pitch p (mm) of the strands meet the following condition (1):0.03.ltoreq.p.ltoreq.W/1000 (1)The radius of curvature R.sub.1 (mm) of the strand at a first side of the screen is determined by the following condition (2)0.5.times.p.ltoreq.R.sub.1 .ltoreq.p (2)The radius of curvature R.sub.2 (mm) of the strand at a second side of the screen meets the following condition(3):R.sub.2 .ltoreq.R.sub.1 (3).

Abstract: A semiconductor memory device such as dynamic random access memories comprises a work line drive circuit provided with two MOS transistors and a word line to which a word line drive signal is supplied, a substrate bias generation circuit for applying a bias voltage to a semiconductor substrate for MOS transistors, a burn-in mode detection circuit for detecting a burn-in test mode signal, and a substrate bias control circuit for controlling the substrate bias generation circuit. When the semiconductor memory device is subjected to a burn-in test, the power supply level Vcc is increased to raise the voltage of the word line drive signal as compared to that at a normal operation. Accordingly, a high level word line drive signal will be applied to cell transistors, thereby performing correct screening thereof.

Abstract: First to third N.sup.+ -type impurity regions are formed separately from one another by a preset distance in the surface area of a P-type semiconductor substrate or a P-well region formed in an N-type semiconductor substrate. The first impurity region is connected to a power source and the second impurity region is connected to a ground terminal. The third impurity region formed between the first and second impurity regions is connected to one end of an input protection resistor which is connected at the other end to a signal input pad.

Abstract: In a semiconductor integrated circuit, power lines or ground lines of a plurality of circuit blocks having equivalent functions are coupled via a switch circuit to a common main power line or main ground line on a semiconductor integrated circuit chip or semiconductor wafer. The main power line is supplied with power source potential and said main ground line with ground potential. A switch control circuit selectively switches the switch circuit ON or OFF so that defective circuit blocks may be deactivated.

Abstract: A control rod has blades each of which includes a neutron absorption region in which neutron absorbers each loaded to the core of a reactor from below and made of absorption nuclear chain type neutron absorber are disposed. The neutron absorption region is divided into two, upper and lower, regions in an axial direction; the boundary between the upper and lower regions is positioned within the range of from 3/8 to 5/8 of the full length of the neutron absorption region in the axial direction from the lower end of the neutron absorption region; and the quantity of the absorption nuclear chain type neutron absorber contained in the lower region in the section perpendicular to the axial direction is smaller than the quantity of the absorption nuclear chain type neutron absorber contained in the upper region in the section perpendicular to the axial direction.

Abstract: Address signals are decoded by partial decoders, to generate in-phase and complementary signals. These signals are selectively input to main decoders consisting of NAND circuits. Further, these signals are fed via through programming fuse elements to a NOR gate. The fuse elements and the NOR gate form a programmable spare decoder. When the bit selected by the main decoder is defective, the output of this main decoder is shut off. Further, the fuse element of the spare decoder is opened corresponding to the main decoder to select the defective bit, thereby to replace the defective bit with the spare bit.

Abstract: A dynamic memory device has a plurality of column unit arrangements. Each of the column unit arrangements includes first and third bit lines connected through first and third switching transistors to a first input terminal of a sense amplifier and second and fourth bit lines connected through second and fourth switching transistors to a second input terminal of the sense amplifier. The other ends of the third and fourth bit lines are connected through fifth and sixth switching transistors to a corresponding data line. A switching control signal cuts off at least one of the first switching transistor group including the first and second switching transistors and the second transistor group including the third and fourth switching transistors during only a given period of time containing time points before and after a time point at which the fifth and sixth switching transistors are turned on when data is written into a memory cell selected from memory cells connected to the bit lines.

Abstract: A method of manufacturing a semiconductor device including the steps of forming a passivation film, which has an opening exposing that region of the interlayer insulation film formed on the fuse element, which corresponds to the region to be melted of fuse element, melting the region of the fuse element to be melted by radiating a laser beam on the exposed region of the interlayer insulation film through the opening, and the step of forming a protective resin layer on the whole main surface of the resultant structure after melting is completed.

Abstract: A semiconductor dynamic memory device includes a plurality of memories, row decoders for selecting the row of the memories, column decoders for selecting the column of memories, and sense amplifier circuits connected to the memories, respectively. The dynamic memory device further has a driving circuit for selectively activating some of the sense amplifier circuits in accordance with the content of a predetermined bit of row address data supplied to the row decoders.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor layer of a second conductivity type opposite to the first conductivity type formed on the substrate. In the layer are formed a first semiconductor region of the first conductivity type, having a low impurity concentration and formed deep; and a second semiconductor region in a surface area of the layer including the surface of the first semiconductor region. The second region has an impurity concentration higher than that of the first region and formed shallower than it. A power source voltage terminal is connected to the substrate and supplies a voltage applied thereto to the second region through the substrate and the layer.

Abstract: An absorption refrigerating system is provided wherein the total circulation flow rate of a diluted solution (absorbing liquid) by pumps is adjustable according to the measured change in the refrigerating load so that the flow rate of the diluted solution is kept at desirable levels to balance with changing refrigerating load.

Abstract: A nonvolatile semiconductor memory device having a gate insulating film with a memory function. An impurity layer having the same conductivity type as that of the substrate region is formed in that substrate region, underlying the gate insulating film having a memory function, in which a channel is formed. The impurity layer has an impurity profile in which a peak of an impurity concentration is in the region distanced by 500 .ANG. or less from the surface of the substrate region and the impurity concentration is 1.times.10.sup.18 cm.sup.-3 or less in the region at the depth of 500 .ANG. or more.

Abstract: The printed circuit board for mounting electronic parts thereon is obtained by transferring flux from a supporting film to the surface of a printed circuit board, and soldering the electronic parts thereto after the supporting film is removed. The supporting film is first coated with the flux, and the flux is transferred to the printed circuit board through the application of heat and pressure. Hot air can be blown from an oblique direction on the flux-coated surface of the printed circuit board after the flux is transferred thereto and before the electronic parts are soldered thereto.This method can provide a uniform flux coat on the printed circuit board and can eliminate various drawbacks which are encountered in conventional approaches in which the surface of the printed circuit board is coated directly with flux in liquid form.

Abstract: A method and an apparatus for detecting failure of nuclear fuel by means of a multi-handle automatic sipper, which comprises a shipper capping operation of mounting a sipper cap of the apparatus for detecting failure of nuclear fuel on the top part of fuel assemblies, an isolation operation of supplying air into the cap after completion of sipper capping operation, thereby forming an air layer, and isolating the fuel assemblies to be detected from other fuel assemblies, a soaking operation of keeping the fuel assemblies in the isolated state for a predetermined period of time, a cell water removal operation of discharging water from system, and a sampling operation of introducing a predetermined amount of cooling water in the fuel assemblies to a sample water receptacle, the operations being provided in sequence, and other operations being carried out in parallel with the aforementioned operations.

Abstract: An apparatus for detecting failure of the nuclear fuel rod has an outer cap and 16 (sixteen) inner caps. In checking for any faulty fuel rods, the outer cap is placed to cover the upper ends of 16 (sixteen) fuel assemblies mounted in the reactor core, while the inner caps in the outer cap are disposed on corresponding one of the fuel assemblies. To the outer cap are attached 4 (four) air supplying hoses. The inner caps receive corresponding one of 16 sampling tubes attached to the outer cap, and coolant sampling hoses are connected to the sampling tubes. A bundle member is fixed to the center of the upper surface of the outer cap. The four air supplying hoses and 16 coolant sampling hoses are fixed to the bundle member. The bundle member has a handle attached thereto.