Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: A method and system for nanoscale precision programmable profiling on substrates. Profiling material is dispensed on a substrate or a superstrate. The superstrate is brought in contact with the substrate. The profiling material is then cured after bringing the superstrate in contact with the substrate. The superstrate is separated from the substrate after curing. An optical metrology of points on the substrate corresponding to the final substrate profile is then performed.

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: A method for introducing a customized variation of a geometric parameter in a nanoscale pattern on a substrate. A nanoscale precision programmable profiling process is conducted on one or more regions of the substrate with the nanoscale pattern, where the nanoscale precision programmable profiling process is used to deposit a profiling film with a thickness profile that is a function of the customized variation of the geometric parameter in the nanoscale pattern. The method further comprises conducting a plasma etch process of the profiling film and the material of the nanoscale pattern that converts the thickness profile of the profiling film into the customized variation of the geometric parameter in the nanoscale pattern, where the customized variation is a function of the thickness profile of the profiling film.

Abstract: A method for fabricating patterns. An inverse optimization scheme is implemented to determine process parameters used to obtain a desired film thickness of a liquid resist formulation, where the liquid resist formulation includes a solvent and one or more non-solvent components. A substrate is covered with a substantially continuous film of the liquid resist formulation using one or more of the following techniques: dispensing discrete drops of a diluted monomer on the substrate using an inkjet and allowing the dispensed drops to spontaneously spread and merge, slot die coating and spin-coating. The liquid resist formulation is diluted in the solvent. The solvent is then substantially evaporated from the liquid resist formulation forming a film. A gap between a template and the substrate is then closed. The film is cured to polymerize the film and the substrate is separated from the template leaving the polymerized film on the substrate.

Abstract: A method for fabricating one or more elements in a multi-lens column. Drops of ultraviolet (UV)-curable liquid are dispensed by an inkjet on a substrate, which may be supported by a chuck. A non-uniform liquid film is then formed, such as by spreading and merging of the inkjetted drops. The film is then locally heated, such as by using a digital micromirror device array. The film is then cured by exposing it to UV light, where the cured film together with the substrate form an element of the multi-lens column. The substrate is then brought to a metrology station where optical metrology is performed on the cured film and the substrate for quality control.

Abstract: A method for fabricating patterns on a flexible substrate in a roll-to-roll configuration. Drops of a monomer diluted in a solvent are dispensed on a substrate, where the drops spontaneously spread and merge with one another to form a liquid resist formulation. The solvent is evaporated (e.g., blanket evaporation) from the liquid resist formulation followed by selective multi-component resist film evaporation resulting in a non-uniform and substantially continuous film on the substrate. The gap between the film on the substrate and a template is closed such that the film fills the features of the template. After cross-linking the film to polymerize the film, the template is separated from the substrate thereby leaving the polymerized film on the substrate.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: A method, computer program product and system for precision inkjet printing. A control variable vector of actuation parameters associated with an inkjet waveform is determined. A printhead is then actuated to eject a grid of droplets from an inkjet onto a substrate based on the inkjet waveform. An image of the grid of droplets on the substrate is acquired. The acquired image is then processed to calculate a fitness function of the inkjet waveform that includes a function of sensed output variables associated with printing characteristics. The control variable vector is then adjusted by updating its topology based on the fitness function to obtain an optimized control variable vector associated with an optimized inkjet waveform.

Abstract: A method and system for nanoscale precision programmable profiling on substrates. Profiling material is dispensed on a substrate or a superstrate. The superstrate is brought in contact with the substrate. The profiling material is then cured after bringing the superstrate in contact with the substrate. The superstrate is separated from the substrate after curing. An optical metrology of points on the substrate corresponding to the final substrate profile is then performed.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

Abstract: A method and system for configuring ultraviolet (UV)-based nanoimprint lithography (NIL) for roll-to-roll (R2R) processing, which combines the benefits of inexpensive R2R processing with the precise nanoscale patterning afforded by NIL. Furthermore, an R2R fabrication process is used to create nanoscale copper (Cu) metal mesh electrodes on flexible polycarbonate substrates and rigid quartz substrates employing jet-and-flash nanoimprint lithography (J-FIL), linear ion source etching (LIS) and selective electroless Cu metallization (ECu) using a palladium (Pd) seed layer.

Abstract: Various embodiments of the present technology generally relate to substrate planarization. More specifically, some embodiments of the present technology relate a versatile systems and methods for precision surface topography optimization known as planarization on nominally planar substrates. In some embodiments, a method for planarization of a patterned substrate using inkjets can determine the global and nanoscale topography and pattern information of the patterned substrate. Based upon the global and nanoscale topography and pattern information, a drop pattern can be determined and then dispensed on the patterned substrate. A gap between the patterned substrate and a superstrate causing the dispensed drops can be closed to form a substantially contiguous film. The substantially contiguous film can be cured and the superstrate can be separated from the patterned substrate with substantially contiguous film on the patterned substrate.

Abstract: A method for fabricating patterns. An inverse optimization scheme is implemented to determine process parameters used to obtain a desired film thickness of a liquid resist formulation, where the liquid resist formulation includes a solvent and one or more non-solvent components. A substrate is covered with a substantially continuous film of the liquid resist formulation using one or more of the following techniques: dispensing discrete drops of a diluted monomer on the substrate using an inkjet and allowing the dispensed drops to spontaneously spread and merge, slot die coating and spin-coating. The liquid resist formulation is diluted in the solvent. The solvent is then substantially evaporated from the liquid resist formulation forming a film. A gap between a template and the substrate is then closed. The film is cured to polymerize the film and the substrate is separated from the template leaving the polymerized film on the substrate.

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

Abstract: A method for fabricating patterns on a flexible substrate in a roll-to-roll configuration. Drops of a monomer diluted in a solvent are dispensed on a substrate, where the drops spontaneously spread and merge with one another to form a liquid resist formulation. The solvent is evaporated (e.g., blanket evaporation) from the liquid resist formulation followed by selective multi-component resist film evaporation resulting in a non-uniform and substantially continuous film on the substrate. The gap between the film on the substrate and a template is closed such that the film fills the features of the template. After cross-linking the film to polymerize the film, the template is separated from the substrate thereby leaving the polymerized film on the substrate.