Abstract: A data processing circuit and a fault-mitigating method are provided. In the method, multiple sub-sequences are divided from sequence data. A first sub-sequence of the sub-sequences is accessed from a memory for a multiply-accumulate (MAC) operation to obtain a first computed result. The MAC operation is performed on a second sub-sequence of the sub-sequences in the memory to obtain a second computed result. The first and the second computed results are combined, where the combined result of the first and the second computed results is related to the result of the MAC operation on the sequence data directly. Accordingly, the error rate could be reduced, so as to mitigate fault.

Abstract: A data processing circuit and a fault mitigating method are provided. The method is adapted for a memory having at least one fault bit. The memory provides a block for data storage. A difference between an output of a value of a plurality of bits input to at least one computing layer in a neural network and a correct value is determined. The bits are respectively considered the at least one fault bit. A repair condition is determined based on the difference. The repair condition includes a correspondence between a position where the fault bit is located in the block and at least one non-fault bit in the memory. A value of at least one non-fault bit of the memory replaces a value of the fault bit based on the repair condition.

Abstract: The present disclosure provides an electronic device including a first sensing circuit, a second sensing circuit and a power line. The first sensing circuit includes a first sensing unit and a first transistor, and a first end of the first sensing unit is coupled to a control end of the first transistor. The second sensing circuit includes a second sensing unit and a second transistor, and a first end of the second sensing unit is coupled to a control end of the second transistor. A first end of the first transistor and a first end of the second transistor are coupled to the power line.

Abstract: This disclosure relates to a combined power module that includes a base structure, a terminal structure, a second terminal, and a cover. The terminal structure includes a mount assembly and a plurality of first terminals. The mount assembly is assembled on the base structure. The first terminals are disposed on the mount assembly. The second terminal is disposed on the base structure. The cover is disposed on the base structure and covers at least part of the first terminals and at least part of the second terminal.

Abstract: Method and apparatus of video coding are disclosed. According to one method, in the decoder side, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block when the neighboring block satisfies one or more conditions. An MPM (Most Probable Mode) list is derived based on information comprising at least one of neighboring Intra modes. A current Intra mode is derived utilizing the MPM list. The current luma block is decoded according to the current Intra mode According to another method, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block if the neighboring block is coded in BDPCM (Block-based Delta Pulse Code Modulation) mode, where the predefined Intra mode is set to horizontal mode or vertical mode depending on prediction direction used by the BDPCM mode.

Abstract: Video processing methods and apparatuses implemented in a video encoding or decoding system with conditional secondary transform signaling. The video encoding system determines and applies a transform operation to residuals of a transform block to generate final transform coefficients, and adaptively signals a secondary transform index according to a position of a last significant coefficient in the transform block. A value of the secondary transform index is determined according to the transform operation.

Abstract: Video processing methods and apparatuses implemented in a video encoding or decoding system with conditional secondary transform signaling. The video encoding system determines and applies a transform operation to residuals of one or more transform blocks to generate final transform coefficients, and skip signaling a secondary transform index if a position of a last significant coefficient in each considered transform block is less than or equal to a predefined position; otherwise, the video encoding system signals a secondary transform index according to the transform operation.

Abstract: A video codec receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video codec signals or parses a first syntax element for a first coding mode in a particular set of two or more coding modes. Each of coding mode of the particular set of coding modes modifies a merge candidate or an inter-prediction that is generated based on the merge candidate. The video codec enables the first coding mode and disables one or more other coding modes in the particular set of coding modes. The disabled one or more coding modes in the particular set of coding modes are disabled without parsing syntax elements for the disabled coding modes. The video codec encodes or decodes the current block by using the enabled first coding mode and bypassing the disabled coding modes.

Abstract: A video decoder that decodes a current block of pixels by using multi-hypothesis combined prediction mode is provided. The video decoder generates a first prediction of the current block based on an inter prediction mode. The video decoder enables the combined prediction mode for the current block based on a block size of the current block determined according to a width and a height of the current block. The combined prediction mode is disabled when the width of or the height of the current block is greater than a threshold length. When the combined prediction mode is enabled, the video decoder generates a second prediction based on an intra prediction mode that is inferred to be a planar mode, and subsequently a combined prediction for the current block based on the first prediction and the second prediction. The video decoder reconstructs the current block by using the combined prediction.

Abstract: A method and apparatus of Inter prediction for video coding using Multi-hypothesis (MH) are disclosed. If an MH mode is used for the current block: at least one MH candidate is derived using reduced reference data by adjusting at least one coding-control setting; an Inter candidate list is generated, where the Inter candidate list comprises said at least one MH candidate; and current motion information associated with the current block is encoded using the Inter candidate list at the video encoder side or the current motion information associated with the current block is decoded at the video decoder side using the Merge candidate list. The coding control setting may correspond to prediction direction setting, filter tap setting, block size of reference block to be fetched, reference picture setting or motion limitation setting.

Abstract: A method and apparatus of Inter prediction for video coding using a target Merge mode comprising a triangle Merge mode are disclosed. According to this method, a current block is partitioned into a first region and a second region using the target partition. A candidate list is determined. Two candidates are determined for the two regions by deriving two target candidates from the candidate list. When a selected target candidate is a uni-prediction candidate, the selected target candidate is used as one candidate; and when the selected target candidate is a bi-prediction candidate, motion information associated of the selected target candidate with List 0 or List 1 is used as one candidate. The current block or current motion information associated with the current block is encoded or decoded according to the candidate list. The candidate list is used to derive the first candidate and the second candidate.

Abstract: Video encoding methods and apparatuses in a video encoding system receive an input residual signal of a current block by a shared transform circuit, apply horizontal transform and vertical transform by a shared transform circuit to generate transform coefficients, apply quantization and inverse quantization to generate recovered transform coefficients, apply inverse vertical transform and inverse horizontal transform to the recovered transform coefficients by the shared transform circuit to generate a reconstructed residual signal for the current block, and encode the current block based on quantized levels of the current block. The shared transform circuit and a coefficient buffer in the folded 4-time transform architecture reuse computation resources in each transform stage. In some embodiments of the folded 4-time transform architecture, a hierarchical design for block size grouping is implemented with fixed throughput for uniform hardware scheduling.

Abstract: Video encoding methods and apparatuses in a video encoding system receive an input residual signal of a current block by a shared transform circuit, apply horizontal transform and vertical transform by a shared transform circuit to generate transform coefficients, apply quantization and inverse quantization to generate recovered transform coefficients, apply inverse vertical transform and inverse horizontal transform to the recovered transform coefficients by the shared transform circuit to generate a reconstructed residual signal for the current block, and encode the current block based on quantized levels of the current block. The shared transform circuit and a coefficient buffer in the folded 4-time transform architecture reuse computation resources in each transform stage. In some embodiments of the folded 4-time transform architecture, a hierarchical design for block size grouping is implemented with fixed throughput for uniform hardware scheduling.

Abstract: A method and apparatus for video coding are disclosed. According to this method, a current block is received at an encoder side or compressed data comprising the current block is received at a decoder side, wherein the current block comprises one luma block and one or more chroma blocks, the current block is generated by partitioning an image area using a single partition tree into one or more partitioned blocks comprising the current block. A target coding mode is determined for the current block. The current block is then encoded or decoded according to the target coding mode, wherein an additional hypothesis of prediction for said one or more chroma blocks is disabled if the target coding mode corresponds to the multi-hypothesis prediction mode and width, height or area of said one or more chroma blocks is smaller than a threshold.

Abstract: Video processing methods and apparatuses for coding a current block generate a final predictor by combining multiple predictors for the current block. A first predictor and a second predictor for the current block are generated by applying one or a combination of settings to the first, second, or both predictors. One or both the first and second predictors are generated from motion compensation. The final predictor is derived from the first and second predictors, and the current block is encoded or decoded according to the final predictor. The settings include supported-mode setting, combined-weight setting, applied-portion setting, motion information setting, precision setting, or a combination of the above settings.

Abstract: Video encoding methods and apparatuses for Sum of Absolute Transformed Difference (SATD) computation by folded Hadamard transform circuits include splitting a current block into SATD blocks, receiving input data associated with a first block of a first SATD block in a first cycle and receiving input data associated with a second block of the first SATD block in a second cycle, and performing calculations for the first block by shared Hadamard transform circuits in the first cycle and performing calculations for the second block by the shared Hadamard transform circuits in the second cycle. Each shared Hadamard transform circuit is a first part of each folded Hadamard transform circuit. The video encoding methods and apparatuses further perform calculations for the entire SATD block by a final part of each folded Hadamard transform circuit to generate a final SATD result of the first SATD block for encoding.

Abstract: A method and apparatus for video coding. According to the method, a set of candidates associated with coding modes or mode parameters are determined. Boundary matching costs associated with the set of candidates are determined, where each of the boundary matching costs is determined for one target candidate of the set of candidates. The costs are calculated by using reconstructed or predicted samples of the current block and one or more neighboring blocks of the current block. Each of the boundary matching costs is calculated using one target configuration selected from a plurality of configurations. A final candidate is selected from the set of candidates based on the boundary matching costs. The current block is encoded or decoded using the final candidate.

Abstract: A video decoder that decodes a current block of pixels by using multi-hypothesis combined prediction mode is provided. The video decoder generates a first prediction of the current block based on an inter prediction mode. The video decoder enables the combined prediction mode for the current block based on a block size of the current block determined according to a width and a height of the current block. The combined prediction mode is disabled when the width of or the height of the current block is greater than a threshold length. When the combined prediction mode is enabled, the video decoder generates a second prediction based on an intra prediction mode that is inferred to be a planar mode, and subsequently a combined prediction for the current block based on the first prediction and the second prediction. The video decoder reconstructs the current block by using the combined prediction.

Abstract: A method and apparatus for predictive coding. According to the method, combined prediction members are determined, where each of the combined prediction member includes a weighted sum of a first prediction candidate and a second prediction candidate using a target weighting selected from a weighting set. Boundary matching costs associated with the combined prediction members are determined, where each of the boundary matching costs is determined, for the combined prediction member with the target weighting, by using predicted samples of the current block based on the combined prediction member with the target weighting and neighbouring reconstructed samples of the current block. The current block is then encoded or decoded using a final combined prediction decided based on at least one of the boundary matching costs.

Abstract: A method and apparatus for video coding. According to this method, a set of candidates associated with coding modes or coding parameters is determined. Boundary matching costs associated with the set of candidates are determined, where each of the boundary matching costs is determined, for one target candidate of the set of candidates, by using reconstructed or predicted samples of the current block and neighbouring reconstructed or predicted samples of the current block. The reconstructed or predicted samples of the current block are determined according to said one target candidate. The set of candidates are reordered according to the boundary matching costs. The current block is then encoded or decoded using a final candidate selected from the set of candidates based on reordered candidates of the set of candidates.