Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.

Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.

Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.

Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.

Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.

Abstract: Formation of copper alloy interconnect lines on integrated circuits includes introducing dopant elements into a copper layer. Copper alloy interconnect lines may be formed by providing a doping layer over a copper layer, driving dopant material into the copper layer with a high temperature step, and polishing the copper layer to form individual lines. Copper alloy interconnect lines may be formed by implanting dopants into individual lines. Copper alloy interconnect lines may be formed by providing a doped seed layer with a capping layer to prevent premature oxidation, forming an overlying copper layer, driving in the dopants, and polishing to form individual lines.

Abstract: A method for forming a material in an opening on a substrate, such as a wafer, using an electron cyclotron resonance-assisted high density plasma physical vapor deposition system. The method comprises the steps of: maintaining a pressure in the range of approximately 1 mTorr to approximately 6 mTorr; generating a plasma by providing a microwave power in the range of approximately 3 kilowatts (kW) to approximately 5 kW; applying a direct current (DC) voltage to a target source of the material in the range of approximately (negative) -600 volts to approximately -1000 volts; providing a current of a predetermined amount to a first electromagnet; and providing a current to a second electromagnet that is less than said predetermined amount, wherein said second electromagnet is disposed below said first electromagnet; and forming a layer of the material in the opening.