Patents by Inventor Shu Kuan
Shu Kuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230378359Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Patent number: 11817499Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: GrantFiled: June 29, 2022Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Publication number: 20230317795Abstract: A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.Type: ApplicationFiled: June 5, 2023Publication date: October 5, 2023Inventors: Shahaji B. More, Shu Kuan, Cheng-Han Lee
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Patent number: 11670681Abstract: A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.Type: GrantFiled: March 19, 2021Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shahaji B. More, Shu Kuan, Cheng-Han Lee
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Publication number: 20220352374Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: ApplicationFiled: June 29, 2022Publication date: November 3, 2022Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Publication number: 20220328621Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Shu KUAN, Shahaji B. MORE, Chien LIN, Cheng-Han LEE, Shih-Chieh CHANG
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Publication number: 20220320321Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.Type: ApplicationFiled: June 17, 2022Publication date: October 6, 2022Inventors: Shahaji B. MORE, Chien LIN, Cheng-Han LEE, Shih-Chieh CHANG, Shu KUAN
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Patent number: 11404574Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: GrantFiled: February 22, 2021Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Patent number: 11393898Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.Type: GrantFiled: July 21, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu Kuan, Shahaji B. More, Chien Lin, Cheng-Han Lee, Shih-Chieh Chang
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Publication number: 20220223690Abstract: A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (b) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.Type: ApplicationFiled: March 19, 2021Publication date: July 14, 2022Inventors: Shahaji B. More, Shu Kuan, Cheng-Han Lee
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Patent number: 11367784Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.Type: GrantFiled: June 15, 2020Date of Patent: June 21, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Chien Lin, Cheng-Han Lee, Shih-Chieh Chang, Shu Kuan
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Publication number: 20210391450Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Inventors: Shahaji B. MORE, Chien LIN, Cheng-Han LEE, Shih-Chieh CHANG, Shu KUAN
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Publication number: 20210273047Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.Type: ApplicationFiled: July 21, 2020Publication date: September 2, 2021Inventors: Shu KUAN, Shahaji B. MORE, Chien LIN, Cheng-Han LEE, Shih-Chieh CHANG
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Publication number: 20210175359Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: ApplicationFiled: February 22, 2021Publication date: June 10, 2021Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Patent number: 10930781Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: GrantFiled: December 11, 2019Date of Patent: February 23, 2021Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Publication number: 20200111911Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: ApplicationFiled: December 11, 2019Publication date: April 9, 2020Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Patent number: 10510889Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: GrantFiled: March 15, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Publication number: 20190165175Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: ApplicationFiled: March 15, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shahaji B. MORE, Huai-Tei YANG, Shih-Chieh CHANG, Shu KUAN, Cheng-Han LEE
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Patent number: 9917189Abstract: A method for detecting the presence and location of defects over a substrate is disclosed. In an embodiment, the method may include: forming a semiconductor material in a plurality of openings in a reference wafer using an epitaxial growth process; performing one or more measurements on the reference wafer to obtain a baseline signal; forming a plurality of gate stacks and stressor regions in a plurality of substrates; after forming the plurality of gate stacks, forming the semiconductor material in a plurality of openings in a batch wafer; performing the one or more measurements on the batch wafer to obtain a batch signal; comparing the batch signal to the baseline signal; and determining whether a defect in present in the plurality of substrates based on the comparison.Type: GrantFiled: July 31, 2015Date of Patent: March 13, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Hung, Chien-Feng Lin, Zheng-Yang Pan, Shu Kuan
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Publication number: 20170033218Abstract: A method for detecting the presence and location of defects over a substrate is disclosed. In an embodiment, the method may include: forming a semiconductor material in a plurality of openings in a reference wafer using an epitaxial growth process; performing one or more measurements on the reference wafer to obtain a baseline signal; forming a plurality of gate stacks and stressor regions in a plurality of substrates; after forming the plurality of gate stacks, forming the semiconductor material in a plurality of openings in a batch wafer; performing the one or more measurements on the batch wafer to obtain a batch signal; comparing the batch signal to the baseline signal; and determining whether a defect in present in the plurality of substrates based on the comparison.Type: ApplicationFiled: July 31, 2015Publication date: February 2, 2017Inventors: Shih-Wei Hung, Chien-Feng Lin, Zheng-Yang Pan, Shu Kuan