Patents by Inventor Shu Ling LIAO

Shu Ling LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240321717
    Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.
    Type: Application
    Filed: June 3, 2024
    Publication date: September 26, 2024
    Inventors: Li-Ling LIAO, Ming-Chih YEW, Chia-Kuei HSU, Shu-Shen YEH, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20240321164
    Abstract: A brightness compensation device includes a panel, a heat detector, a memory, and a processor. he processor is configured to perform the following steps: at a specific grayscale of the red grayscale data, the green grayscale data, or the blue grayscale data, adjusting a turn-on time data of a luminous signal according to the first temperature data; adjusting the red grayscale data, the green grayscale data, or the blue grayscale data according to a brightness relation or the sheet to obtain a red updating grayscale data, a green updating grayscale data, or a blue updating grayscale data; and when it is determined that the second temperature data is the same as the first temperature data, outputting or storing the red updating grayscale data, the green updating grayscale data, or the blue updating grayscale data.
    Type: Application
    Filed: October 30, 2023
    Publication date: September 26, 2024
    Inventors: Shu-Wen LIAO, Ti-Kuei YU, Yen-Wen FANG, Ya-Ling HSU
  • Publication number: 20240258100
    Abstract: Fabrication of semiconductor devices is provided. A chamber is evacuated to a pressure of less than about 1 Torr. The chamber is heated to a temperature in excess of about 400° C. A precursor is introduced into the chamber. The precursor is decomposed with a first plasma. A first layer is deposited on a surface of the semiconductor device based on the decomposed precursor. The precursor is densified to form a first gate spacer. The precursor is introduced into the chamber subsequent to forming the first layer. The precursor is decomposed with a second plasma. A second layer is deposited on the surface of the semiconductor device based on the decomposed precursor. The deposited precursor is densified to form a second gate spacer.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ling Liao, Te-En Cheng, Nai-Yu Yeh, Ming-Han Chung, Chunyao Wang, Yung-Cheng LU
  • Publication number: 20240250069
    Abstract: A package structure is provided. The package structure includes a chip structure having opposite surfaces with different widths. The chip structure has an inclined sidewall between the opposite surfaces. The package structure also includes a protective layer laterally surrounding the chip structure.
    Type: Application
    Filed: April 2, 2024
    Publication date: July 25, 2024
    Inventors: Shu-Shen YEH, Po-Chen LAI, Che-Chia YANG, Li-Ling LIAO, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20240242661
    Abstract: A display device includes first and second pixel circuits, first and second gate lines, and first and second transmission lines. The first pixel circuit emits light according to a data signal, and is charged according to a first gate signal. The second pixel circuit emits light according to the data signal, and is charged according to a second gate signal. The first gate line is located between the first second pixel circuits, and provides the first gate signal. The second gate line provides the second gate signal. The first transmission line provides the second gate signal to the second gate line. The second transmission line is located between the first transmission line and the second pixel circuit, crosses over the second gate line, and provides the first gate signal to the first gate line.
    Type: Application
    Filed: July 7, 2023
    Publication date: July 18, 2024
    Inventors: Yueh-Chi WU, Shu-Wen LIAO, Ti-Kuei YU, Ya-Ling HSU, Sheng-Yen CHENG, Yueh-Hung CHUNG
  • Patent number: 12040267
    Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.
    Type: Grant
    Filed: March 14, 2023
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Li-Ling Liao, Ming-Chih Yew, Chia-Kuei Hsu, Shu-Shen Yeh, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240153828
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Shu Ling Liao, Chung-Chi Ko
  • Patent number: 11908750
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu Ling Liao, Chung-Chi Ko
  • Publication number: 20230326746
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 12, 2023
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Publication number: 20230317448
    Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.
    Type: Application
    Filed: June 9, 2023
    Publication date: October 5, 2023
    Inventors: Shu Ling Liao, Chung-Chi Ko, Wan-Yi Kao
  • Patent number: 11715637
    Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu Ling Liao, Chung-Chi Ko, Wan-Yi Kao
  • Patent number: 11705327
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Publication number: 20230155006
    Abstract: Semiconductor devices including fin-shaped isolation structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; a shallow trench isolation (STI) region over the semiconductor substrate adjacent the fin; and a dielectric fin structure over the STI region, the dielectric fin structure extending in a direction parallel to the fin, the dielectric fin structure including a first liner layer in contact with the STI region; and a first fill material over the first liner layer, the first fill material including a seam disposed in a lower portion of the first fill material and separated from a top surface of the first fill material, a first carbon concentration in the lower portion of the first fill material being greater than a second carbon concentration in an upper portion of the first fill material.
    Type: Application
    Filed: May 13, 2022
    Publication date: May 18, 2023
    Inventors: Wan-Yi Kao, Fang-Yi Liao, Shu Ling Liao, Yen-Chun Huang, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20230135509
    Abstract: A semiconductor device and a method of forming the same are provided. A device includes a substrate, a first isolation structure over the substrate, a first fin and a second fin over the substrate and extending through the first isolation structure, and a hybrid fin extending into the first isolation structure and interposed between the first fin and the second fin. A top surface of the first fin and a top surface of the second fin are above a top surface of the first isolation structure. A top surface of the hybrid fin is above the top surface of the first isolation structure. The hybrid fin includes an upper region, and a lower region under the upper region. The lower region includes a seam. A topmost portion of the seam is below the top surface of the first fin and the top surface of the second fin.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 4, 2023
    Inventors: Yen-Chun Huang, Shu Ling Liao, Fang-Yi Liao, Yu-Chang Lin
  • Publication number: 20220230871
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Publication number: 20220157596
    Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.
    Type: Application
    Filed: February 2, 2022
    Publication date: May 19, 2022
    Inventors: Shu Ling Liao, Chung-Chi Ko, Wan-Yi Kao
  • Patent number: 11295948
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 11244823
    Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu Ling Liao, Chung-Chi Ko, Wan-Yi Kao
  • Publication number: 20210287948
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Shu Ling Liao, Chung-Chi Ko
  • Publication number: 20210202235
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao