Patents by Inventor Shu Ling LIAO

Shu Ling LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11295948
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 11244823
    Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu Ling Liao, Chung-Chi Ko, Wan-Yi Kao
  • Publication number: 20210287948
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Shu Ling Liao, Chung-Chi Ko
  • Publication number: 20210202235
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 11024550
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu Ling Liao, Chung-Chi Ko
  • Patent number: 10950431
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 10748760
    Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu Ling Liao, Chung-Chi Ko, Wan-Yi Kao
  • Publication number: 20200058561
    Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.
    Type: Application
    Filed: February 14, 2019
    Publication date: February 20, 2020
    Inventors: Shu Ling Liao, Chung-Chi Ko
  • Publication number: 20200027719
    Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Shu Ling Liao, Chung-Chi Ko, Wan-Yi Kao
  • Publication number: 20190279863
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Publication number: 20190164743
    Abstract: Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.
    Type: Application
    Filed: August 10, 2018
    Publication date: May 30, 2019
    Inventors: Shu Ling Liao, Chung-Chi Ko, Wan-Yi Kao
  • Patent number: 10304677
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Publication number: 20190103265
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Application
    Filed: April 13, 2018
    Publication date: April 4, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi KAO, Chung-Chi KO, Li Chun TE, Hsiang-Wei LIN, Te-En CHENG, Wei-Ken LIN, Guan-Yao TU, Shu Ling LIAO