Patents by Inventor Shu-Ting Tsai
Shu-Ting Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250120209Abstract: The problem of forming a deep trench isolation structure suitable for photodetectors with small pitch is solved by a process in which a grid of trenches is etched from the front side using high energy plasma followed by annealing. The trenches are filled with an oxide followed by etching to recess the oxide. The trench recesses are filled with semiconductor to form a grid-shaped semiconductor structure. After FEOL processing, BEOL processing, attachment to a second substrate, and thinning from the back side, an etch removes the oxide from the back side. The etch stops on the grid-shaped semiconductor structure. The trenches are then lined and filled from the back side. The front side etch allows the trenches to be made narrow and with highly vertical sidewalls. Lining and filling the trenches from the back side provides good optical and electrical isolation.Type: ApplicationFiled: October 4, 2023Publication date: April 10, 2025Inventors: Shu-Ting Tsai, Tzu-Jui Wang, U-Ting Chen, Shyh-Fann Ting, Szu-Ying Chen
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Patent number: 11916091Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate.Type: GrantFiled: April 15, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
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Patent number: 11915977Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.Type: GrantFiled: April 12, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
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Publication number: 20240038818Abstract: Some implementations described herein provide for techniques to form a biased backside deep trench isolation and grid structure for a backside illumination image sensor. The techniques include forming an array of backside deep trench isolation structures and a biasing-pad that electrically connects to the array of metal-filled backside deep trench isolation structures through the grid structure. The array of backside deep trench isolation structures, the grid structure, and the biasing-pad structure may reduce a likelihood of electrical cross-talk and/or oblique light cross-talk between the photodiodes of the backside illumination image sensor. In this way, a performance of the backside illumination image sensor may be improved. Such improvements may include a suppression of a dark current within the backside illumination image sensor, a reduction in a number of white pixels, and a reduction in cross-talk within the backside illumination image sensor.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Inventors: Y.W. HUANG, Chen-Hsien LIN, U-Ting CHEN, Shu-Ting TSAI, Tzu-Hsuan HSU
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Publication number: 20230378139Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.Type: ApplicationFiled: July 26, 2023Publication date: November 23, 2023Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Chia-Chieh Lin, U-Ting Chen
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Patent number: 11798916Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.Type: GrantFiled: July 30, 2018Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Chia-Chieh Lin, U-Ting Chen
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Patent number: 11769781Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a photodetector disposed in a semiconductor substrate. An interlayer dielectric (ILD) structure is disposed on a first side of the semiconductor substrate. A storage node is disposed in the semiconductor substrate and spaced from the photodetector, where the storage node is spaced from the first side by a first distance. A first isolation structure is disposed in the semiconductor substrate and between the photodetector and the storage node, where the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate that is opposite the first side, and where the first isolation structure is spaced from the first side by a second distance that is less than the first distance.Type: GrantFiled: May 19, 2021Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Tzu-Hsuan Hsu
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Publication number: 20230201613Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
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Patent number: 11596800Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.Type: GrantFiled: June 15, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
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Publication number: 20220208749Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width.Type: ApplicationFiled: March 16, 2022Publication date: June 30, 2022Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Szu-Ying Chen, U-Ting Chen
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Patent number: 11315972Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.Type: GrantFiled: November 12, 2020Date of Patent: April 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
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Publication number: 20210272989Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a photodetector disposed in a semiconductor substrate. An interlayer dielectric (ILD) structure is disposed on a first side of the semiconductor substrate. A storage node is disposed in the semiconductor substrate and spaced from the photodetector, where the storage node is spaced from the first side by a first distance. A first isolation structure is disposed in the semiconductor substrate and between the photodetector and the storage node, where the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate that is opposite the first side, and where the first isolation structure is spaced from the first side by a second distance that is less than the first distance.Type: ApplicationFiled: May 19, 2021Publication date: September 2, 2021Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Tzu-Hsuan Hsu
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Publication number: 20210233945Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate.Type: ApplicationFiled: April 15, 2021Publication date: July 29, 2021Inventors: Hung-Wen Hsu, Jiech-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
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Publication number: 20210233813Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.Type: ApplicationFiled: April 12, 2021Publication date: July 29, 2021Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
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Patent number: 11018177Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a photodetector disposed in a semiconductor substrate. An interlayer dielectric (ILD) structure is disposed on a first side of the semiconductor substrate. A storage node is disposed in the semiconductor substrate and spaced from the photodetector, where the storage node is spaced from the first side by a first distance. A first isolation structure is disposed in the semiconductor substrate and between the photodetector and the storage node, where the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate that is opposite the first side, and where the first isolation structure is spaced from the first side by a second distance that is less than the first distance.Type: GrantFiled: August 30, 2019Date of Patent: May 25, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Tzu-Hsuan Hsu
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Patent number: 11011567Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.Type: GrantFiled: November 8, 2019Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jeng-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
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Patent number: 10978345Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.Type: GrantFiled: October 4, 2018Date of Patent: April 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
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Publication number: 20210066357Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.Type: ApplicationFiled: November 12, 2020Publication date: March 4, 2021Inventors: Hung-Wen Hsu, Jieh-Fun Lu, Yeur-Luen Tu, U-Ting Chen, Shu-Ting Tsai, Hsiu-Yu Cheng
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Patent number: 10861899Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.Type: GrantFiled: December 20, 2019Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
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Publication number: 20200381465Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a photodetector disposed in a semiconductor substrate. An interlayer dielectric (ILD) structure is disposed on a first side of the semiconductor substrate. A storage node is disposed in the semiconductor substrate and spaced from the photodetector, where the storage node is spaced from the first side by a first distance. A first isolation structure is disposed in the semiconductor substrate and between the photodetector and the storage node, where the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate that is opposite the first side, and where the first isolation structure is spaced from the first side by a second distance that is less than the first distance.Type: ApplicationFiled: August 30, 2019Publication date: December 3, 2020Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Tzu-Hsuan Hsu