Patents by Inventor Shu-Wei Kuo

Shu-Wei Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240164008
    Abstract: A molded electronic assembly including a circuit substrate, a plurality of electronic devices, and at least one patterned heat dissipation structure is provided. The circuit substrate includes a substrate and a circuit, where the substrate has a top surface, and the circuit has a plurality of signal contacts distributed on the top surface. The electronic devices are disposed on the circuit substrate, and each of the electronic devices has a plurality of device pins connected to the signal contacts. The at least one patterned heat dissipation structure corresponds to a signal contact of the signal contacts and starts from the corresponding signal contact and extends toward a plurality of directions on the top surface of the substrate.
    Type: Application
    Filed: November 10, 2023
    Publication date: May 16, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Li-Wei Yao, Hsiao-Fen Wei, Chung-Wei Wang, Shu-Wei Kuo
  • Patent number: 11646259
    Abstract: Provided is a forming method of a redistribution structure including: forming a first redistribution layer and a first compensation circuit layer on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer, and the first compensation circuit layer and the first redistribution layer are electrically insulated from each other; forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; and forming a second redistribution layer and a second compensation circuit layer on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer and the second redistribution layer are electrically insulated from each other, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: May 9, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Wei Kuo, Chen-Tsai Yang, Wei-Yuan Cheng, Chien-Hsun Chu, Shau-Fei Cheng
  • Patent number: 11329500
    Abstract: A charging-and-discharging device and a charging-and-discharging method are provided. The charging-and-discharging device includes a renewable energy converter, an aluminum battery, a controller and a current converter. The renewable energy converter receives a power from a renewable energy power generation system. The controller is coupled to the renewable energy converter and the aluminum battery, wherein the controller configures a charging-and-discharging power of the aluminum battery, according to a power value of the power, to compensate the power so as to generate a compensated power. The current converter is coupled to the controller, wherein the current converter outputs the compensated power to a power grid after performing DC/AC converting.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: May 10, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Wei Kuo, Chang-Chung Yang
  • Publication number: 20220130744
    Abstract: Provided is a forming method of a redistribution structure including: forming a first redistribution layer and a first compensation circuit layer on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer, and the first compensation circuit layer and the first redistribution layer are electrically insulated from each other; forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; and forming a second redistribution layer and a second compensation circuit layer on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer and the second redistribution layer are electrically insulated from each other, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer.
    Type: Application
    Filed: January 26, 2021
    Publication date: April 28, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Shu-Wei Kuo, Chen-Tsai Yang, Wei-Yuan Cheng, Chien-Hsun Chu, Shau-Fei Cheng
  • Publication number: 20200244094
    Abstract: A charging-and-discharging device and a charging-and-discharging method are provided. The charging-and-discharging device includes a renewable energy converter, an aluminum battery, a controller and a current converter. The renewable energy converter receives a power from a renewable energy power generation system. The controller is coupled to the renewable energy converter and the aluminum battery, wherein the controller configures a charging-and-discharging power of the aluminum battery, according to a power value of the power, to compensate the power so as to generate a compensated power. The current converter is coupled to the controller, wherein the current converter outputs the compensated power to a power grid after performing DC/AC converting.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 30, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Shu-Wei Kuo, Chang-Chung Yang
  • Patent number: 10573587
    Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: February 25, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Wei Kuo, Chun-Yi Cheng, Wei-Yuan Cheng
  • Patent number: 10522438
    Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 31, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Chun-Yi Cheng, Wei-Yuan Cheng, Shu-Wei Kuo, Yu-Jhen Yang
  • Patent number: 10461035
    Abstract: A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 29, 2019
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shu-Wei Kuo, Wei-Yuan Cheng, Chen-Tsai Yang, Jie-Mo Lin
  • Patent number: 10366965
    Abstract: A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place module and an alignment module. The pick and place module is suitable for picking up and placing the chip. The alignment module is movably connected to the pick and place module. The alignment module includes at least one alignment protrusion, wherein the at least one alignment protrusion extends toward at least one alignment socket included in the redistribution structure. Furthermore, a chip bonding method and a chip package structure are provided.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 30, 2019
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shu-Wei Kuo, Wei-Yuan Cheng, Shau-Fei Cheng
  • Publication number: 20190131271
    Abstract: A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place module and an alignment module. The pick and place module is suitable for picking up and placing the chip. The alignment module is movably connected to the pick and place module. The alignment module includes at least one alignment protrusion, wherein the at least one alignment protrusion extends toward at least one alignment socket included in the redistribution structure. Furthermore, a chip bonding method and a chip package structure are provided.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 2, 2019
    Applicants: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shu-Wei Kuo, Wei-Yuan Cheng, Shau-Fei Cheng
  • Patent number: 10249567
    Abstract: A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a first surface of the dielectric layer, at least one lower conductive wire disposed on a second surface of the dielectric layer, and vias penetrating the dielectric layer and connecting the at least one upper conductive wire and the at least one lower conductive wire. Each via has a cross-section at one upper conductive wire. The cross-section has a third width. The ratio of the third width to the thickness of the dielectric layer is less than or equal to 1. The ratio of the pitch between every two adjacent vias to the third width is greater than or equal to 0.5.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: April 2, 2019
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Jie-Mo Lin, Shu-Wei Kuo, Wei-Yuan Cheng, Chen-Tsai Yang
  • Publication number: 20190088600
    Abstract: A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.
    Type: Application
    Filed: December 20, 2017
    Publication date: March 21, 2019
    Applicants: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shu-Wei Kuo, Wei-Yuan Cheng, Chen-Tsai Yang, Jie-Mo Lin
  • Publication number: 20190057934
    Abstract: A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a first surface of the dielectric layer, at least one lower conductive wire disposed on a second surface of the dielectric layer, and vias penetrating the dielectric layer and connecting the at least one upper conductive wire and the at least one lower conductive wire. Each via has a cross-section at one upper conductive wire. The cross-section has a third width. The ratio of the third width to the thickness of the dielectric layer is less than or equal to 1. The ratio of the pitch between every two adjacent vias to the third width is greater than or equal to 0.5.
    Type: Application
    Filed: December 25, 2017
    Publication date: February 21, 2019
    Applicants: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Jie-Mo Lin, Shu-Wei Kuo, Wei-Yuan Cheng, Chen-Tsai Yang
  • Publication number: 20180122694
    Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.
    Type: Application
    Filed: May 16, 2017
    Publication date: May 3, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Chun-Yi Cheng, Wei-Yuan Cheng, Shu-Wei Kuo, Yu-Jhen Yang
  • Publication number: 20180122732
    Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.
    Type: Application
    Filed: August 10, 2017
    Publication date: May 3, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Shu-Wei Kuo, Chun-Yi Cheng, Wei-Yuan Cheng
  • Patent number: 9743513
    Abstract: According to embodiments of the disclosure, a flexible electronic device is provided. The flexible electronic device includes a flexible substrate, at least one component and at least one stress buffer. The component may be disposed on the flexible substrate and having a lateral surface. The stress buffer may be disposed adjacent to the lateral surface of the component and has a stiffness which is getting larger toward the component.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: August 22, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shu-Wei Kuo, Kuo-Lung Lo, Cheng-Che Wu, Chen-Chu Tsai
  • Publication number: 20160192478
    Abstract: According to embodiments of the disclosure, a flexible electronic device is provided. The flexible electronic device includes a flexible substrate, at least one component and at least one stress buffer. The component may be disposed on the flexible substrate and having a lateral surface. The stress buffer may be disposed adjacent to the lateral surface of the component and has a stiffness which is getting larger toward the component.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shu-Wei KUO, Kuo-Lung LO, Cheng-Che WU, Chen-Chu TSAI
  • Patent number: 9069250
    Abstract: A method for manufacturing an electrowetting display unit includes the following steps. A first substrate and a second substrate are provided. A first conductive layer is disposed on one side of the first substrate. A second conductive layer is disposed on one side of the second substrate. A polymer layer, which includes a siloxane containing a light-induced cross linkable group and a Si—H bond, is disposed on the first conductive layer. The molecular weight of the monomer of the siloxane is equal to or greater than 5000. A part of the polymer layer is exposed to a light so as to form a plurality of hydrophobic sections. A hydrophilic section is developed by treating a developing agent. The hydrophilic section and the plurality of hydrophobic sections form a pattern layer together. Polar liquid and non-polar liquid are disposed between the pattern layer and the second conductive layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 30, 2015
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Chun Liu, Shu-Wei Kuo, Ping-Chen Chen
  • Patent number: 9046681
    Abstract: The disclosure provides an electro-wetting element, including: a first substrate and a second substrate, wherein the first substrate and the second substrate are disposed oppositely; a first electrode formed on the first substrate; a photoreactive layer formed on the first electrode, wherein the photoreactive layer includes a reversible photoreactive material; a second electrode formed on the first substrate or the second substrate; and a polar fluid and a non-polar fluid disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: June 2, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Wei Kuo, Yi-Chun Liu, Wei-Yuan Cheng
  • Patent number: 8830558
    Abstract: The disclosure provides an electrowetting display device. The electrowetting display device includes a first substrate and a second substrate disposed to each other. A first electrode layer may dispose on the first substrate. A second electrode layer may dispose on the second substrate. A hydrophobic dielectric layer is disposed on the first electrode layer. A first pixel rib is disposed on the first substrate. A second pixel rib is disposed on the first pixel rib. A water contact angle of the second pixel rib may be larger than that of the first pixel rib. A first liquid and a second liquid may be disposed in between the first substrate and the second substrate.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: September 9, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Wei Kuo, Yun-Sheng Ku, Wei-Yuan Cheng, Pei-Pei Cheng