Patents by Inventor Shu-Yen Chan
Shu-Yen Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11770924Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.Type: GrantFiled: February 6, 2023Date of Patent: September 26, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
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Publication number: 20230189498Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
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Patent number: 11631679Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.Type: GrantFiled: May 10, 2022Date of Patent: April 18, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
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Patent number: 11502180Abstract: A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.Type: GrantFiled: February 17, 2020Date of Patent: November 15, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chia-Wei Wu, Ting-Pang Chung, Tien-Chen Chan, Shu-Yen Chan
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Publication number: 20220271037Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.Type: ApplicationFiled: May 10, 2022Publication date: August 25, 2022Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
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Patent number: 11393826Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.Type: GrantFiled: October 31, 2018Date of Patent: July 19, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
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Patent number: 10847517Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including of an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.Type: GrantFiled: June 18, 2019Date of Patent: November 24, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tsuo-Wen Lu, Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
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Publication number: 20200185505Abstract: A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.Type: ApplicationFiled: February 17, 2020Publication date: June 11, 2020Inventors: Chia-Wei Wu, Ting-Pang Chung, Tien-Chen Chan, Shu-Yen Chan
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Patent number: 10608086Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate, at least one active area is defined on the substrate, a buried word line is disposed in the substrate, a source/drain region disposed beside the buried word line, a diffusion barrier region, disposed at the top of the source/drain region, the diffusion barrier region comprises a plurality of doping atoms selected from the group consisting of carbon atoms, nitrogen atoms, germanium atoms, oxygen atoms, helium atoms and xenon atoms, a dielectric layer disposed on the substrate, and a contact structure disposed in the dielectric layer, and electrically connected to the source/drain region.Type: GrantFiled: December 27, 2017Date of Patent: March 31, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
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Patent number: 10608093Abstract: A semiconductor device and a method of forming the same are disclosed. First, a substrate having a main surface is provided. At least a trench is formed in the substrate. A barrier layer is formed in the trench and a conductive material is formed on the barrier layer and filling up the trench. The barrier layer and the conductive material are then recessed to be lower than the upper surface of the substrate. After that, an oxidation process is performed to oxidize the barrier layer and the conductive material thereby forming an insulating layer.Type: GrantFiled: January 18, 2018Date of Patent: March 31, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chia-Wei Wu, Ting-Pang Chung, Tien-Chen Chan, Shu-Yen Chan
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Patent number: 10497704Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.Type: GrantFiled: December 20, 2018Date of Patent: December 3, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Ger-Pin Lin, Kuan-Chun Lin, Chi-Mao Hsu, Shu-Yen Chan, Shih-Fang Tzou, Tsuo-Wen Lu, Tien-Chen Chan, Feng-Yi Chang, Shih-Kuei Yen, Fu-Che Lee
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Publication number: 20190312036Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including of an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.Type: ApplicationFiled: June 18, 2019Publication date: October 10, 2019Inventors: Tsuo-Wen Lu, Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
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Patent number: 10373958Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.Type: GrantFiled: January 22, 2018Date of Patent: August 6, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tsuo-Wen Lu, Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
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Patent number: 10332889Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.Type: GrantFiled: April 12, 2018Date of Patent: June 25, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan, Chi-Mao Hsu, Shih-Fang Tzou, Ting-Pang Chung, Chia-Wei Wu
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Publication number: 20190181141Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench.Type: ApplicationFiled: October 31, 2018Publication date: June 13, 2019Inventors: Luo-Hsin Lee, Ting-Pang Chung, Shih-Han Hung, Po-Han Wu, Shu-Yen Chan, Shih-Fang Tzou
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Publication number: 20190164977Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.Type: ApplicationFiled: December 20, 2018Publication date: May 30, 2019Inventors: Ger-Pin Lin, Kuan-Chun Lin, Chi-Mao Hsu, Shu-Yen Chan, Shih-Fang Tzou, Tsuo-Wen Lu, Tien-Chen Chan, Feng-Yi Chang, Shih-Kuei Yen, Fu-Che Lee
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Publication number: 20190074280Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.Type: ApplicationFiled: April 12, 2018Publication date: March 7, 2019Inventors: Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan, Chi-Mao Hsu, Shih-Fang Tzou, Ting-Pang Chung, Chia-Wei Wu
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Publication number: 20190067293Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.Type: ApplicationFiled: September 21, 2017Publication date: February 28, 2019Inventors: Ger-Pin Lin, Kuan-Chun Lin, Chi-Mao Hsu, Shu-Yen Chan, Shih-Fang Tzou, Tsuo-Wen Lu, Tien-Chen Chan, Feng-Yi Chang, Shih-Kuei Yen, Fu-Che Lee
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Patent number: 10217750Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.Type: GrantFiled: September 21, 2017Date of Patent: February 26, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Ger-Pin Lin, Kuan-Chun Lin, Chi-Mao Hsu, Shu-Yen Chan, Shih-Fang Tzou, Tsuo-Wen Lu, Tien-Chen Chan, Feng-Yi Chang, Shih-Kuei Yen, Fu-Che Lee
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Publication number: 20190035792Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.Type: ApplicationFiled: January 22, 2018Publication date: January 31, 2019Inventors: Tsuo-Wen Lu, Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan