Abstract: A microstrip line structure includes a conductive ground plane having a strip opening encircled by the ground plane. The strip opening extends from a top surface to a bottom surface of the ground plane. The microstrip line structure further includes a dielectric strip filling the strip opening; a dielectric layer over and contacting the ground plane; and a signal line over the dielectric layer, wherein the signal line has a portion directly above a portion of the dielectric strip, and wherein the signal line and the dielectric strip are non-parallel.

Abstract: A device that includes a coplanar waveguide structure is disclosed. In an example, a device includes a coplanar waveguide structure that is oriented in a first direction, and a slot-type floating shield structure oriented proximate to the coplanar waveguide structure. The slot-type floating shield structure includes a first portion that extends transversely to the coplanar waveguide structure in a second direction and a second portion that extends from the first portion in a third direction that is perpendicular to the first direction and the second direction.

Abstract: Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures.

Abstract: A coupled microstrip line structure having tunable characteristic impedance and wavelength are provided. In accordance with one aspect of the invention, a coupled microstrip line structure comprises a first ground plane having a plurality of first conductive strips separated by a dielectric material, and a first dielectric layer over the first ground plane. The coupled microstrip line further comprises a first signal line over the first dielectric layer, wherein the first signal line is directly above the plurality of first conductive strips, and wherein the first signal line and the plurality of first conductive strips are non-parallel, and a second signal line over the first dielectric layer, wherein the second signal line is directly above the plurality of first conductive strips, and wherein the second signal line and the plurality of first conductive strips are non-parallel, and wherein the second signal line is substantially parallel to the first signal line.

Abstract: A device that includes a coplanar waveguide structure is disclosed. In an example, a device includes a coplanar waveguide structure that is oriented in a first direction, and a slot-type floating shield structure oriented proximate to the coplanar waveguide structure. The slot-type floating shield structure includes a first portion that extends transversely to the coplanar waveguide structure in a second direction and a second portion that extends from the first portion in a third direction that is perpendicular to the first direction and the second direction.

Abstract: An integrated circuit structure includes an interconnect structure over a semiconductor substrate and a coaxial transmission line. The coaxial transmission line includes a signal line, a top plate over the signal line and electrically insulated from the signal line, and a bottom plate under the signal line and electrically insulated from the signal line. At least one of the top plate and the bottom plate includes metal strip shields and dielectric strips, with each of the dielectric strips being between two of the metal strip shields. The integrated circuit structure further includes a ground conductor electrically connecting the top plate and the bottom plate. The ground conductor is insulated from the signal line by a dielectric material.

Abstract: A semiconductor device for transmitting a radio frequency signal along a signal line includes a signal line that extends along a principal axis. On one side of the signal line is a first dielectric, and on the opposite side of the signal line is a second dielectric. First and second ground lines are proximate to the first and second dielectrics, respectively, and the ground lines are approximately parallel to the signal line. The device has a transverse cross-section that varies along the principal axis.

Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate; a first dielectric layer over the semiconductor substrate and in the interconnect structure; a second dielectric layer in the interconnect structure and over the first dielectric layer; and a wave-guide. The wave-guide includes a first portion in the first dielectric layer and a second portion in the second dielectric layer. The first portion adjoins the second portion.

Abstract: Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures.

Abstract: A device including a coplanar waveguide structure is disclosed. A coplanar waveguide structure comprises one or more ground lines proximate to one or more signal lines, the signal lines and the ground lines being essentially parallel to each other and oriented substantially along a first direction; a periodic structure included in at least one of the one or more signal lines comprises alternating segments, wherein at least one of the alternating segments extends in a second direction transverse to the first direction.

Abstract: A coupled microstrip line structure having tunable characteristic impedance and wavelength are provided. In accordance with one aspect of the invention, a coupled microstrip line structure comprises a first ground plane having a plurality of first conductive strips separated by a dielectric material, and a first dielectric layer over the first ground plane. The coupled microstrip line further comprises a first signal line over the first dielectric layer, wherein the first signal line is directly above the plurality of first conductive strips, and wherein the first signal line and the plurality of first conductive strips are non-parallel, and a second signal line over the first dielectric layer, wherein the second signal line is directly above the plurality of first conductive strips, and wherein the second signal line and the plurality of first conductive strips are non-parallel, and wherein the second signal line is substantially parallel to the first signal line.

Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate; a first dielectric layer over the semiconductor substrate and in the interconnect structure; a second dielectric layer in the interconnect structure and over the first dielectric layer; and a wave-guide. The wave-guide includes a first portion in the first dielectric layer and a second portion in the second dielectric layer. The first portion adjoins the second portion.

Abstract: An integrated circuit structure includes an interconnect structure over a semiconductor substrate and a coaxial transmission line. The coaxial transmission line includes a signal line, a top plate over the signal line and electrically insulated from the signal line, and a bottom plate under the signal line and electrically insulated from the signal line. At least one of the top plate and the bottom plate includes metal strip shields and dielectric strips, with each of the dielectric strips being between two of the metal strip shields. The integrated circuit structure further includes a ground conductor electrically connecting the top plate and the bottom plate. The ground conductor is insulated from the signal line by a dielectric material.

Abstract: A microstrip line structure includes a conductive ground plane having a strip opening encircled by the ground plane. The strip opening extends from a top surface to a bottom surface of the ground plane. The microstrip line structure further includes a dielectric strip filling the strip opening; a dielectric layer over and contacting the ground plane; and a signal line over the dielectric layer, wherein the signal line has a portion directly above a portion of the dielectric strip, and wherein the signal line and the dielectric strip are non-parallel.

Abstract: A semiconductor device for transmitting a radio frequency signal along a signal line includes a signal line that extends along a principal axis. On one side of the signal line is a first dielectric, and on the opposite side of the signal line is a second dielectric. First and second ground lines are proximate to the first and second dielectrics, respectively, and the ground lines are approximately parallel to the signal line. The device has a transverse cross-section that varies along the principal axis.

Abstract: Shield structures are provided. A first and second shield lines are formed over a substrate and coupled with a first voltage. A conductive line is formed between the first and the second shield lines, and coupled with a second voltage. The first shield layer is formed over the substrate and coupled to the first and the second shield lines via at least one first conductive structure.

Abstract: A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S/D regions. The etch stop layer maintains a high dopant concentration in deep S/D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.

Abstract: A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S/D regions. The etch stop layer maintains a high dopant concentration in deep S/D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.

Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.

Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.