Patents by Inventor Shubhendu Mukherjee

Shubhendu Mukherjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7849387
    Abstract: In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: December 7, 2010
    Assignee: Intel Corporation
    Inventors: Arijit Biswas, Niranjan Soundararajan, Shubhendu Mukherjee
  • Publication number: 20090271676
    Abstract: In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.
    Type: Application
    Filed: April 23, 2008
    Publication date: October 29, 2009
    Inventors: Arijit Biswas, Niranjan Soundararajan, Shubhendu Mukherjee
  • Publication number: 20070260820
    Abstract: A technique for demand-based error correction. More particularly, at least one embodiment of the invention relates to a technique to reduce storage overhead of cache memories containing error correction codes (ECC) while maintaining substantially the same performance of the cache.
    Type: Application
    Filed: February 27, 2006
    Publication date: November 8, 2007
    Inventors: Moinuddin Qureshi, Paul Racunas, Shubhendu Mukherjee
  • Publication number: 20070250755
    Abstract: In accordance with some embodiments, an error checking scheme to check for an error in a memory unit during a dormant state is provided herein.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 25, 2007
    Inventors: Wayne Burleson, Mondira Pant, Shubhendu Mukherjee
  • Patent number: 7260674
    Abstract: A parallel lookup memory (PLM) is provided. The PLM includes a content addressable memory (CAM) array having a plurality of CAM entries. Each CAM entry has at least two storage location, and one of the locations includes value matching logic. The PLM also includes a PLM controller, which, responsive to an external command, applies a search value to a sub-set of the CAM entries. The sub-set and search values are identified by the external command, which includes data identifying CAM entries that are a start and end location of the sub-set, or data identifying a CAM entries that is a start of the sub-set and a length identifier representing a number of CAM entries to be searched. The PLM may be provided in a processor core, in a processor chip external to a processor core as a counterpart to a layer of cache, or in a multiprocessor computer system having a number of agents coupled to an external communication bus, where the PLM is provided in a first agent and a processor is provided in a second agent.
    Type: Grant
    Filed: May 25, 2004
    Date of Patent: August 21, 2007
    Assignee: Intel Corporation
    Inventor: Shubhendu Mukherjee
  • Publication number: 20070168712
    Abstract: Methods of operating two or more devices in lockstep by generating requests at each device, comparing the requests, and forwarding matching requests to a servicing node are described and claimed. A redundant execution system using the methods is also described and claimed.
    Type: Application
    Filed: November 18, 2005
    Publication date: July 19, 2007
    Inventors: Paul Racunas, Matthew Mattina, George Chrysos, Shubhendu Mukherjee
  • Publication number: 20070079036
    Abstract: Methods and apparatus to reduce power consumption in arbiters of interconnection routers are described. In one embodiment, an arbiter may be turned off for a select number of clock cycles if no arbitration is to be performed on the corresponding buffer.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventor: Shubhendu Mukherjee
  • Publication number: 20070076622
    Abstract: A network may include an interconnection system which allows packets to transit from various sources to various destinations under control of routers. The routers may determine a transit time of packet transit from various sources to a given destination. This information may be used to detect a hot spot within the network. Other embodiments are described and claimed.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventor: Shubhendu Mukherjee
  • Publication number: 20070022348
    Abstract: Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core matches a value from the corresponding structure in the other core. The global checker is to detect lockstep failures between the two cores. The fault logic is to cause the two cores to be resynchronized if there is a lockstep error but the micro-checker has detected a mismatch.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 25, 2007
    Inventors: Paul Racunas, Joel Emer, Arijit Biswas, Shubhendu Mukherjee, Steven Raasch
  • Publication number: 20070011513
    Abstract: Embodiments of apparatuses and methods for selective activation of error mitigation based on bit level error counts are disclosed. In one embodiment, an apparatus includes a plurality of state elements, an error counter, and activation logic. The error counter is to count the number of bit level errors in the state elements. The activation logic is to increase error mitigation if the number of bit level errors exceeds a threshold value.
    Type: Application
    Filed: June 13, 2005
    Publication date: January 11, 2007
    Inventors: Arijit Biswas, Steven Raasch, Shubhendu Mukherjee
  • Publication number: 20060156155
    Abstract: In one embodiment, the present invention includes a system, which may be a multiprocessor system having multiple nodes, each with a processor and a cache. The system may include a directory stored in a memory that includes entries having coherency information. At least one of the nodes may be configured to detect an error in an entry of the directory based on a coherency protocol. In some embodiments, the node may correct the error using state information obtained from other nodes. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2004
    Publication date: July 13, 2006
    Inventors: Sudhanva Gurumurthi, Arijit Biswas, Joel Emer, Shubhendu Mukherjee
  • Publication number: 20060156123
    Abstract: A method for a fault free store data path in a software implementation of redundant multithreading environments is described. In one embodiment, after a check is performed by a hardware/software checker, the processor still needs to ensure that the data just checked reaches protected memory without any faults. The present implementation provides sufficient redundant information along the path of a store from register read to commit, such that it may detect any single bit upset error in the path.
    Type: Application
    Filed: December 22, 2004
    Publication date: July 13, 2006
    Inventors: Shubhendu Mukherjee, Robert Cohn
  • Publication number: 20060156153
    Abstract: An error handling routine of a processor, executing in response to a first detected unrecoverable error (DUE) of the processor, responding to an indication that a second DUE has occurred by evaluating the effect of the second DUE on the correctness of the error handling routine.
    Type: Application
    Filed: December 14, 2004
    Publication date: July 13, 2006
    Inventors: Tryggve Fossum, Yaron Shragai, Shubhendu Mukherjee
  • Publication number: 20060149940
    Abstract: A method and apparatus for enabling a processor to perform a save and restore on a context switch incrementally and on demand. In one embodiment, when OS switches to a new process, the processor saves only those registers that have been modified in the current process. The processor may not bring in these registers for the new process, rather, the processor will load them on demand. If instructions from the new process do not locate their source operand in the register file, it will initiate a miss handling flow for the register and restore the register value in the register file. Then the pipeline will reissue the instruction that missed in the register file.
    Type: Application
    Filed: December 27, 2004
    Publication date: July 6, 2006
    Inventor: Shubhendu Mukherjee
  • Publication number: 20060150048
    Abstract: A method and apparatus for protecting a TLB's VPN from soft errors is described. On a TLB lookup, the incoming virtual address is used to CAM the TLB VPN. In parallel with this CAM operation, parity is computed on the incoming virtual address for the possible page sizes supported by the processor. If a matching VPN is found in the TLB, its payload is read out. The encoded page size is used to select which of the set of pre-computed virtual address parity to compare with the stored parity bit in the TLB entry. This has the advantage of removing the computation of parity on the TLB VPN from the critical path of the TLB lookup. Instead it is now in the TLB fill path.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Inventors: Ugonna Echeruo, George Chrysos, John Crawford, Shubhendu Mukherjee
  • Publication number: 20060143551
    Abstract: In one embodiment, the present invention includes a method of detecting and correcting an error by detecting the error in a circuit coupled to a first stage of a semiconductor device, and correcting the error in the circuit using valid data present in the circuit. The circuit may be a scan cell, in some embodiments. In such manner, errors may be corrected locally, minimizing the impact of the error on performance and power consumption. Other embodiments are described and claimed.
    Type: Application
    Filed: December 29, 2004
    Publication date: June 29, 2006
    Inventors: Arijit Biswas, Steven Raasch, Shubhendu Mukherjee, Subhasish Mitra
  • Publication number: 20060123195
    Abstract: Embodiments of the present invention are generally directed to a method, apparatus and system for a computing system implementing a technique known as cache push. The cache push technique enhances a single writer invalidation protocol with the ability to optionally push data into another processor's cache without changing the memory consistency model.
    Type: Application
    Filed: December 6, 2004
    Publication date: June 8, 2006
    Inventor: Shubhendu Mukherjee
  • Publication number: 20060095821
    Abstract: A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.
    Type: Application
    Filed: September 29, 2004
    Publication date: May 4, 2006
    Inventors: Shubhendu Mukherjee, Joel Emer, Steven Reinhardt, Christopher Weaver
  • Publication number: 20060075301
    Abstract: An apparatus includes a buffer that collects store instruction information associated with one or more processes. The collected store instruction information includes data and addresses where the data are to be stored. The apparatus also includes a buffer control that drains the buffer of store instructions associated with a first process before it collects store instructions associated with a second process.
    Type: Application
    Filed: September 24, 2004
    Publication date: April 6, 2006
    Inventors: Tryggve Fossum, Yaron Shragai, Ugonna Echeruo, Shubhendu Mukherjee
  • Publication number: 20060075300
    Abstract: A processor includes a process identifier unit to assign process identifiers to one or more processes executed by the processor. The processor also includes an error detector to detect errors in the processor and an error posting unit to post process identifiers and error information associated with the detected errors.
    Type: Application
    Filed: September 23, 2004
    Publication date: April 6, 2006
    Inventor: Shubhendu Mukherjee