Abstract: An apparatus includes a buffer that collects store instruction information associated with one or more processes. The collected store instruction information includes data and addresses where the data are to be stored. The apparatus also includes a buffer control that drains the buffer of store instructions associated with a first process before it collects store instructions associated with a second process.

Abstract: A method and apparatus for packet coalescing within interconnection network routers. In one embodiment, the method includes the scan of at least one input buffer to identify at least two network packets that include coherence protocol messages and are directed to the same destination, but from different sources. In one embodiment, coherence protocol messages within the network packets are combined into a coalesced network packet. Once combined, the coalesced network packet is transmitted to the same or matching destination. In one embodiment, combining multiple network packets (each containing a single logical coherence message) into a larger, coalesced network packet amortizes the fixed overhead of sending a network packet including a single coherence message, as compared to the larger, coalesced network packet, to improve bandwidth usage. Other embodiments are described and claimed.

Abstract: A technique to reduce false error detection in microprocessors by tracking dynamically dead instructions. When an instruction commits, it is then stored in a PET buffer. A processor may now declare a machine check error when the instruction is being removed from the PET buffer rather than at the commit point. The processor can scan the PET buffer to determine if the instruction is a dynamically dead instruction. This further enables the processor to reduce false positives.

Abstract: A technique to reduce false error detection in microprocessors by tracking instructions neutral to errors. As an instruction is decoded, an anti-pi bit is tagged to the decoded instruction. When a parity error is detected, an instruction queue first checks if the anti-pi bit is set. If the anti-pi bit is set, then instruction is neutral to errors, and the pi bit need not be set. Prefetch, branch predict hint and NOP are types of instructions that are neutral to errors.

Abstract: A technique to reduce false error detection in microprocessors. A pi bit is propagated with an instruction through an instruction flow path. When a parity error is detected, the pi bit is set, instead of raising a machine check exception. Upon reaching a commit point, the processor can determine if the instruction was on a wrong path.

Abstract: A technique to reduce false error detection in microprocessors within a redundant multi-threaded computing environment. A pi bit is propagated with at least two instructions through an instruction flow path. Results of executing the instruction are compared to see if an error has occurred and if so, the pi bits are examined to determine which instruction contains the error.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a first central processing unit (CPU) having a translation buffer (TB) to store virtual to physical address translations, and a snoop filter coupled to the first CPU to mirror the operation of the first TB and implemented to search for entries upon receiving an invalidation request from a second CPU.

Abstract: A parallel lookup memory (PLM) is provided. The PLM includes a content addressable memory (CAM) array having a plurality of CAM entries. Each CAM entry has at least two storage location, and one of the locations includes value matching logic. The PLM also includes a PLM controller, which, responsive to an external command, applies a search value to a sub-set of the CAM entries. The sub-set and search values are identified by the external command, which includes data identifying CAM entries that are a start and end location of the sub-set, or data identifying a CAM entries that is a start of the sub-set and a length identifier representing a number of CAM entries to be searched. The PLM may be provided in a processor core, in a processor chip external to a processor core as a counterpart to a layer of cache, or in a multiprocessor computer system having a number of agents coupled to an external communication bus, where the PLM is provided in a first agent and a processor is provided in a second agent.

Abstract: The ability to combine a plurality of remote read miss requests and/or a plurality of exclusive access requests into a single network packet for efficiently utilizing network bandwidth. This combination exists for a plurality of processors in a network configuration. In contrast, other solutions have inefficiently utilized network bandwidth by individually transmitting a plurality of remote read miss requests and/or a plurality of exclusive access requests via a plurality of network packets.

Abstract: A multithreaded architecture is disclosed for buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support. In particular, the performance of a SRT processor is enhanced by using speculative memory support to buffer the leading threads stores until they can be compared with their trailing thread counterparts. Buffering these stores in the memory system allows them to be removed from the store buffer. Since the speculative memory system will have greater capacity than the store buffer, additional stores may be buffered before the leading thread will be forced to stall. This will result in an increase in slack between threads, and thus an increase in performance.

Abstract: A multithreaded architecture is disclosed for managing external memory updates for fault detection in redundant multithreading systems using speculative memory support. In particular, a method provides input replication of load values on a SRT processor by using speculative memory support to isolate redundant threads form external updates. This method thus avoids the need for dedicated structures to provide input replication.

Abstract: A multithreaded architecture having one or more checker circuits that operate on store operations that send data outside of a sphere of replication. Fault detection mechanisms used to check outputs from the sphere of replication are reused for checkpointing at the conclusion of an execution epoch.

Abstract: Methods and apparatuses for incremental, periodic storage of checkpoints in a multi-threaded processor.

Abstract: Log-based hardware recovery. A checkpointed state of a system includes both architectural register values and memory. The checkpoint consists of a copy of the architectural register file values at the time the checkpoint is generated. An ordered log of non-deterministic events is maintained so that the responses can be repeated to simulate a complete checkpoint for error recovery purposes. When a processor detects an error, the processor reloads the state from the last checkpoint and repeats the non-deterministic events from the log.