Patents by Inventor Shubhendu S. Mukherjee

Shubhendu S. Mukherjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10042778
    Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 7, 2018
    Assignee: Cavium, Inc.
    Inventors: Shubhendu S. Mukherjee, Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis
  • Publication number: 20170206171
    Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.
    Type: Application
    Filed: March 31, 2017
    Publication date: July 20, 2017
    Inventors: Shubhendu S. Mukherjee, Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis
  • Patent number: 9645941
    Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 9, 2017
    Assignee: CAVIUM, INC.
    Inventors: Shubhendu S. Mukherjee, Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis
  • Patent number: 9639476
    Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 2, 2017
    Assignee: CAVIUM, INC.
    Inventors: Bryan W. Chin, Shubhendu S. Mukherjee, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler
  • Patent number: 9501425
    Abstract: Each of multiple translation lookaside buffers (TLBs) is associated with a corresponding processing element. A first TLB invalidation (TLBI) instruction is issued at a first processing element, and sent to a second processing element. An element-specific synchronization instruction is issued at the first processing element. A synchronization command is broadcast, and received at the second processing element. The element-specific synchronization instruction prevents issuance of additional TLBI instructions at the first processing element until an acknowledgement in response to the synchronization command is received at the first processing element.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: November 22, 2016
    Assignee: Cavium, Inc.
    Inventors: Shubhendu S. Mukherjee, David Asher, Mike Bertone, Bradley Dobbie, Thomas Hummel
  • Patent number: 9390023
    Abstract: According to at least one example embodiment, a method and corresponding apparatus for conditionally storing data include initiating an atomic sequence by executing, by a core processor, an instruction/operation designed to initiate an atomic sequence. Executing the instruction designed to initiate the atomic sequence includes loading content associated with a memory location into a first cache memory, and maintaining an indication of the memory location and a copy of the corresponding content loaded. A conditional storing operation is then performed, the conditional storing operation includes a compare-and-swap operation, executed by a controller associated with a second cache memory, based on the maintained copy of the content and the indication of the memory location.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: July 12, 2016
    Assignee: Cavium, Inc.
    Inventors: Richard E. Kessler, David H. Asher, Michael Sean Bertone, Shubhendu S. Mukherjee, Wilson P. Snyder, II, John M. Perveiler, Christopher J. Comis
  • Patent number: 9323715
    Abstract: According to at least one example embodiment, a method and corresponding processor device comprise maintaining a translation data structure mapping uncompressed process context identifiers to corresponding compressed identifiers, the uncompressed process context identifiers and the corresponding compressed identifiers being associated with address spaces or corresponding computer processes. The compressed identifiers are employed to probe, or access, one or more structures of the processor device in executing an operation associated with a computer process.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: April 26, 2016
    Assignee: Cavium, Inc.
    Inventors: Shubhendu S. Mukherjee, Michael S. Bertone, David A. Carlson
  • Patent number: 9268694
    Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: February 23, 2016
    Assignee: Cavium, Inc.
    Inventors: Wilson P. Snyder, II, Bryan W. Chin, Shubhendu S. Mukherjee, Michael Bertone, Richard E. Kessler
  • Patent number: 9081688
    Abstract: In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: July 14, 2015
    Assignee: Intel Corporation
    Inventors: Glenn J. Hinton, Steven E. Raasch, Sebastien Hily, John G. Holm, Ronak Singhal, Avinash Sodani, Deborah T. Marr, Shubhendu S. Mukherjee, Arijit Biswas, Adrian C. Moga
  • Publication number: 20150134931
    Abstract: According to at least one example embodiment, a method and corresponding processor device comprise maintaining a translation data structure mapping uncompressed process context identifiers to corresponding compressed identifiers, the uncompressed process context identifiers and the corresponding compressed identifiers being associated with address spaces or corresponding computer processes. The compressed identifiers are employed to probe, or access, one or more structures of the processor device in executing an operation associated with a computer process.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: Cavium, Inc.
    Inventors: Shubhendu S. Mukherjee, Michael S. Bertone, David A. Carlson
  • Publication number: 20150100737
    Abstract: According to at least one example embodiment, a method and corresponding apparatus for conditionally storing data include initiating an atomic sequence by executing, by a core processor, an instruction/operation designed to initiate an atomic sequence. Executing the instruction designed to initiate the atomic sequence includes loading content associated with a memory location into a first cache memory, and maintaining an indication of the memory location and a copy of the corresponding content loaded. A conditional storing operation is then performed, the conditional storing operation includes a compare-and-swap operation, executed by a controller associated with a second cache memory, based on the maintained copy of the content and the indication of the memory location.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: Cavium, Inc.
    Inventors: Richard E. Kessler, David H. Asher, Michael Sean Bertone, Shubhendu S. Mukherjee, Wilson P. Snyder, II, John M. Perveiler, Christopher J. Comis
  • Publication number: 20150089147
    Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: Cavium, Inc.
    Inventors: Wilson P. Snyder, II, Bryan W. Chin, Shubhendu S. Mukherjee, Michael Bertone, Richard E. Kessler
  • Publication number: 20150089116
    Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: Cavium, Inc.
    Inventors: Bryan W. Chin, Shubhendu S. Mukherjee, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler
  • Publication number: 20150089184
    Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: Cavium, Inc.
    Inventors: Shubhendu S. Mukherjee, Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis
  • Patent number: 8914672
    Abstract: An apparatus and method is described herein for replacing faulty core components. General purpose hardware is provided to replace core pipeline components, such as execution units. In the embodiment of execution unit replacement, a proxy unit is provided, such that mapping logic is able to map instruction/operations, which correspond to faulty execution units, to the proxy unit. As a result, the proxy unit is able to receive the operations, send them to general purpose hardware for execution, and subsequently write-back the execution results to a register file; it essentially replaces the defective execution unit allowing a processor with defective units to be sold or continue operation.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Steven E. Raasch, Michael D. Powell, Shubhendu S. Mukherjee, Arijit Biswas
  • Patent number: 8291394
    Abstract: A method for detecting transient fault includes translating binary code to an intermediate language code. An instruction of interest in the intermediate language code is identified. Reliability instructions are inserted in the intermediate language code to validate values from the instruction of interest. The intermediate language code is translated to binary code. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: George A. Reis, Robert Cohn, Shubhendu S. Mukherjee
  • Patent number: 8171328
    Abstract: Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: May 1, 2012
    Assignee: Intel Corporation
    Inventors: Shubhendu S. Mukherjee, Arijit Biswas, Paul B. Racunas, Steven E. Raasch
  • Publication number: 20110271262
    Abstract: A method for detecting transient fault includes translating binary code to an intermediate language code. An instruction of interest in the intermediate language code is identified. Reliability instructions are inserted in the intermediate language code to validate values from the instruction of interest. The intermediate language code is translated to binary code. Other embodiments are described and claimed.
    Type: Application
    Filed: July 13, 2011
    Publication date: November 3, 2011
    Inventors: George A. Reis, Robert Cohn, Shubhendu S. Mukherjee
  • Patent number: 8024715
    Abstract: A method for detecting transient fault includes translating binary code to an intermediate language code. An instruction of interest in the intermediate language code is identified. Reliability instructions are inserted in the intermediate language code to validate values from the instruction of interest. The intermediate language code is translated to binary code. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: September 20, 2011
    Assignee: Intel Corporation
    Inventors: George A. Reis, Robert Cohn, Shubhendu S. Mukherjee
  • Publication number: 20110161630
    Abstract: An apparatus and method is described herein for replacing faulty core components. General purpose hardware is provided to replace core pipeline components, such as execution units. In the embodiment of execution unit replacement, a proxy unit is provided, such that mapping logic is able to map instruction/operations, which correspond to faulty execution units, to the proxy unit. As a result, the proxy unit is able to receive the operations, send them to general purpose hardware for execution, and subsequently write-back the execution results to a register file; it essentially replaces the defective execution unit allowing a processor with defective units to be sold or continue operation.
    Type: Application
    Filed: December 28, 2009
    Publication date: June 30, 2011
    Inventors: Steven E. Raasch, Michael D. Powell, Shubhendu S. Mukherjee, Arijit Biswas