Abstract: Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.

Abstract: Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.

Abstract: Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.

Abstract: Communicating among multiple sets of multiples cores includes: buffering messages in first buffer associated with a first set of multiple cores; buffering messages in a second buffer associated with a second set of multiple cores; and transferring messages over communication circuitry from cores not in the first set to the first buffer, and to transferring messages from cores not in the second set to the second buffer. A first core of the first set sends messages corresponding to multiple types of instructions to a second core of the second set through the communication circuitry. The second buffer is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores in the first set at the same time, and still have enough storage space for one or more instructions of a first type.

Abstract: A translation lookaside buffer stores information indicating respective page sizes for different translations. A virtual-address cache module manages entries, where each entry stores a memory block in association with a virtual address and a code representing at least one page size of a memory page on which the memory block is located. The managing includes: receiving a translation lookaside buffer invalidation instruction for invalidating at least one translation lookaside buffer entry in the translation lookaside buffer, where the translation lookaside buffer invalidation instruction includes at least one invalid virtual address; comparing selected bits of the invalid virtual address with selected bits of each of a plurality of virtual addresses associated with respective entries in the virtual-address cache module, based on the codes; and invalidating one or more entries in the virtual-address cache module based on the comparing.

Abstract: Managing memory access requests for a plurality of processor cores includes: storing admission control information for determining whether or not to admit a predetermined type of memory access request into a shared resource that is shared among the processor cores and includes one or more cache levels of a hierarchical cache system and at least one memory controller for accessing a main memory; determining whether or not a memory access request of the predetermined type made on behalf of a first processor core should be admitted into the shared resource based at least in part on the stored admission control information; and updating the admission control information based on a latency of a response to a particular memory access request admitted into the shared resource, where the updating depends on whether the response originated from a particular cache level included in the shared resource or from the main memory.

Abstract: Managing memory access requests to a cache system including one or more cache levels that are configured to store cache lines that correspond to memory blocks in a main memory includes: storing stream information identifying recognized streams that were recognized based on previously received memory access requests, where one or more of the recognized streams comprise strided streams that each have an associated strided prefetch result corresponding to a stride that is larger than or equal to a size of a single cache line; and determining whether or not a next cache line prefetch request corresponding to a particular memory access request will be made based at least in part on whether or not the particular memory access request matches a strided prefetch result for at least one strided stream, and a history of past next cache line prefetch requests.

Abstract: A virtual-address cache module receives at least a portion of a virtual address and in response indicates a hit or a miss. A first cache structure stores only memory blocks with virtual addresses that are members of a set of multiple synonym virtual addresses that have all been previously received by the virtual-address cache module during the operating period, where each member of a particular set of multiple synonym virtual addresses translates to a common physical address, and a memory block with the common physical address is stored in at most a single storage location within the first cache structure. A second cache structure stores only memory blocks with virtual addresses that do not have any synonym virtual addresses that have been previously received by the virtual-address cache during the operating period.

Abstract: Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs) consisting of fewer than all VAs associated with a first set of translation context (TC) values, searching VA-indexed structure(s) to find and invalidate any entries that correspond to a VA in the subset; in response to determining that a second IM applies to all VAs associated with a second set of TC values and that no entry exists in invalidation-tracking structure(s) corresponding to the second set, bypassing searching any VA-indexed structure(s); and in response to determining that a third IM applies to all VAs associated with a third set of TC values and that at least one entry exists in the invalidation-tracking structure(s) corresponding to the third set, storing invalidation information in the invalidation-tracking structure(s) to invalidate the third set and delaying searching any VA-indexed structure(s).

Abstract: Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs) consisting of fewer than all VAs associated with a first set of translation context (TC) values, searching VA-indexed structure(s) to find and invalidate any entries that correspond to a VA in the subset; in response to determining that a second IM applies to all VAs associated with a second set of TC values and that no entry exists in invalidation-tracking structure(s) corresponding to the second set, bypassing searching any VA-indexed structure(s); and in response to determining that a third IM applies to all VAs associated with a third set of TC values and that at least one entry exists in the invalidation-tracking structure(s) corresponding to the third set, storing invalidation information in the invalidation-tracking structure(s) to invalidate the third set and delaying searching any VA-indexed structure(s).

Abstract: A virtual-address cache module receives at least a portion of a virtual address and in response indicates a hit or a miss. A first cache structure stores only memory blocks with virtual addresses that are members of a set of multiple synonym virtual addresses that have all been previously received by the virtual-address cache module during the operating period, where each member of a particular set of multiple synonym virtual addresses translates to a common physical address, and a memory block with the common physical address is stored in at most a single storage location within the first cache structure. A second cache structure stores only memory blocks with virtual addresses that do not have any synonym virtual addresses that have been previously received by the virtual-address cache during the operating period.

Abstract: Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses; translating from the intermediate physical addresses to physical addresses; determining reuse information for memory pages based on estimated reuse of cache lines of data stored within the memory pages; storing the determined reuse information independently from: (1) any bits used to indicate virtual addresses, (2) any bits used to indicate intermediate physical addresses, and (3) any bits used to indicate physical addresses; and using the stored reuse information to store cache lines in a selected group of multiple groups of cache lines of a first cache.

Abstract: A filter includes filter entries, each corresponding to a mapping between a virtual memory address and a physical memory address and including a presence indicator indicative which processing elements have the mapping present in their respective translation lookaside buffers (TLBs). A TLB invalidation (TLBI) instruction is received for a first mapping. If a first filter entry corresponding to the first mapping exists in the filter, the plurality of processing elements are partitioned into a first partition of zero or more processing elements that have the first mapping present in their TLBs and a second partition of zero or more processing elements that do not have the first mapping present in their TLBs based on the presence indicator of the first filter entry. The TLBI instruction is sent to the processing elements included in the first partition, and not those in the second partition.

Abstract: Managing a plurality of translation lookaside buffers (TLBs) includes: issuing, at a first processing element, a first instruction for invalidating one or more TLB entries associated with a first context in a first TLB associated with the first processing element. The issuing includes: determining whether or not a state of an indicator indicates that all TLB entries associated with the first context in a second TLB associated with a second processing element are invalidated; if not: sending a corresponding instruction to the second processing element, causing invalidation of all TLB entries associated with the first context in the second TLB, and changing a state of the indicator; and if so: suppressing sending of any corresponding instructions for causing invalidation of any TLB entries associated with the first context in the second TLB to the second processing element.

Abstract: A motherboard includes multiple sockets, each socket configured to accept an integrated circuit. A first integrated circuit in a first socket includes one or more cores and at least one buffer. A second integrated circuit in a second socket includes one or more cores and at least one buffer. Communication circuitry transfers messages to buffers of integrated circuits coupled to different sockets. A first core on the first integrated circuit is configured to send messages corresponding to multiple types of instructions to a second core on the second integrated circuit through the communication circuitry. The buffer of the second integrated circuit is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores on the first integrated circuit at the same time, and still have enough storage space for one or more instructions of a first type.

Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.

Abstract: At least one CPU is configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. At the second access level, translating uses mappings in a first page table; and, at the second access level, class information is determined for a memory page mapped by the first page table based on a classification of virtual addresses. At the first access level, translating uses mappings in a second page table; and, at the first access level, class information is determined for the memory page mapped by the second page table based on a classification of intermediate physical addresses. The class information determined at either access level is independent from certain bits used to indicate addresses. Class information determined at different access levels is processed to determine processed class information for the memory page using a dynamic processing rule.

Abstract: At least one CPU is configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. At the second access level, translating uses mappings in a first page table; and, at the second access level, class information is determined for a memory page mapped by the first page table based on a classification of virtual addresses. At the first access level, translating uses mappings in a second page table; and, at the first access level, class information is determined for the memory page mapped by the second page table based on a classification of intermediate physical addresses. The class information determined at either access level is independent from certain bits used to indicate addresses. Class information determined at different access levels is processed to determine processed class information for the memory page using a dynamic processing rule.

Abstract: Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses using mappings in a first page table accessed by the guest operating system; translating from the intermediate physical addresses to physical addresses using mappings in a second page table accessed by the hypervisor; determining reuse information for a second memory page mapped by both the first page table and the second page table based on estimated reuse of data stored within the second memory page; storing the determined reuse information in both the first page table and the second page table; and using the stored reuse information to store cache lines in selected portions of a first cache.

Abstract: Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses; translating from the intermediate physical addresses to physical addresses; determining reuse information for memory pages based on estimated reuse of cache lines of data stored within the memory pages; storing the determined reuse information independently from: (1) any bits used to indicate virtual addresses, (2) any bits used to indicate intermediate physical addresses, and (3) any bits used to indicate physical addresses; and using the stored reuse information to store cache lines in a selected group of multiple groups of cache lines of a first cache.