Patents by Inventor Shuhei Nakata
Shuhei Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10886372Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery below and horizontally overlapping a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: GrantFiled: July 30, 2019Date of Patent: January 5, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura
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Patent number: 10858757Abstract: An epitaxial substrate includes a single-crystal substrate of silicon carbide, and an epitaxial layer of silicon carbide disposed on the single-crystal substrate. The epitaxial layer includes a first epitaxial layer disposed on the single-crystal substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The first epitaxial layer has a basal-plane-dislocation conversion rate of less than 95%. The second epitaxial layer has a basal-plane-dislocation conversion rate of more than 98%.Type: GrantFiled: May 9, 2017Date of Patent: December 8, 2020Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Takanori Tanaka, Shigehisa Yamamoto, Yu Nakamura, Yasuhiro Kimura, Shuhei Nakata, Yoichiro Mitani
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Publication number: 20190355821Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: ApplicationFiled: July 30, 2019Publication date: November 21, 2019Applicant: Mitsubishi Electric CorporationInventors: Yukiyasu NAKAO, Masayuki IMAIZUMI, Shuhei NAKATA, Naruhisa MIURA
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Patent number: 10418444Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: GrantFiled: April 4, 2014Date of Patent: September 17, 2019Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura
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Publication number: 20190145021Abstract: An epitaxial substrate includes a single-crystal substrate of silicon carbide, and an epitaxial layer of silicon carbide disposed on the single-crystal substrate. The epitaxial layer includes a first epitaxial layer disposed on the single-crystal substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The first epitaxial layer has a basal-plane-dislocation conversion rate of less than 95%. The second epitaxial layer has a basal-plane-dislocation conversion rate of more than 98%.Type: ApplicationFiled: May 9, 2017Publication date: May 16, 2019Applicant: Mitsubishi Electric CorporationInventors: Takanori TANAKA, Shigehisa YAMAMOTO, Yu NAKAMURA, Yasuhiro KIMURA, Shuhei NAKATA, Yoichiro MITANI
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Patent number: 10062758Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.Type: GrantFiled: August 19, 2014Date of Patent: August 28, 2018Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Hiroshi Watanabe
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Patent number: 9525057Abstract: A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.Type: GrantFiled: March 12, 2013Date of Patent: December 20, 2016Assignee: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Shiro Hino, Akihiko Furukawa, Yuji Abe, Shuhei Nakata, Masayuki Imaizumi, Yasuhiro Kagawa
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Patent number: 9502553Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side of the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first well, the second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.Type: GrantFiled: July 1, 2015Date of Patent: November 22, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Naoki Yutani
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Patent number: 9293572Abstract: In a high speed switching power semiconductor device having a sense pad, a high voltage is generated during switching operations in well regions under the sense pad due to a displacement current flowing through its flow path with a resistance, whereby the power semiconductor device sometimes breaks down by dielectric breakdown of a thin insulating film such as a gate insulating film. In a power semiconductor device according to the invention, sense-pad well contact holes are provided on well regions positioned under the sense pad and penetrate a field insulating film thicker than the gate insulating film to connect to the source pad, thereby improving reliability.Type: GrantFiled: June 24, 2010Date of Patent: March 22, 2016Assignee: Mitsubishi Electric CorporationInventors: Akihiko Furukawa, Yasuhiro Kagawa, Naruhisa Miura, Shiro Hino, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Masayuki Imaizumi
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Patent number: 9202940Abstract: A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.Type: GrantFiled: July 31, 2012Date of Patent: December 1, 2015Assignee: Mitsubishi Electric CorporationInventors: Tsuyoshi Kawakami, Yoshiyuki Nakaki, Yoshio Fujii, Hiroshi Watanabe, Shuhei Nakata, Kohei Ebihara, Akihiko Furukawa
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Publication number: 20150303297Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.Type: ApplicationFiled: July 1, 2015Publication date: October 22, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa MIURA, Shuhei NAKATA, Kenichi OHTSUKA, Shoyu WATANABE, Naoki YUTANI
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Patent number: 9105715Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.Type: GrantFiled: April 30, 2009Date of Patent: August 11, 2015Assignee: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Naoki Yutani
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Patent number: 9059086Abstract: A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (d) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.Type: GrantFiled: June 9, 2011Date of Patent: June 16, 2015Assignee: Mitsubishi Electric CorporationInventors: Yuji Ebiike, Takahiro Nakatani, Hiroshi Watanabe, Yoshio Fujii, Sunao Aya, Yoshiyuki Nakaki, Tsuyoshi Kawakami, Shuhei Nakata
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Publication number: 20150108564Abstract: A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well region; and a source resistance control region arranged between the source extension region and the source contact region. The source resistance control region is different in an impurity concentration from the source extension region and the source contact region. These three regions are connected in series between the source pad and the channel region in the well region.Type: ApplicationFiled: March 12, 2013Publication date: April 23, 2015Applicant: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Shiro Hino, Akihiko Furukawa, Yuji Abe, Shuhei Nakata, Masayuki Imaizumi, Yasuhiro Kagawa
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Patent number: 9006819Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.Type: GrantFiled: February 8, 2011Date of Patent: April 14, 2015Assignee: Mitsubishi Electric CorporationInventors: Shiro Hino, Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Akihiko Furukawa, Yukiyasu Nakao, Masayuki Imaizumi
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Publication number: 20140353686Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.Type: ApplicationFiled: August 19, 2014Publication date: December 4, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Hiroshi Watanabe
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Patent number: 8860039Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.Type: GrantFiled: April 7, 2011Date of Patent: October 14, 2014Assignee: Mitsubishi Electric CorporationInventors: Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Hiroshi Watanabe
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Publication number: 20140299888Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: ApplicationFiled: April 4, 2014Publication date: October 9, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yukiyasu NAKAO, Masayuki IMAIZUMI, Shuhei NAKATA, Naruhisa MIURA
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Publication number: 20140203393Abstract: A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings.Type: ApplicationFiled: July 31, 2012Publication date: July 24, 2014Applicant: Mitsubishi Electric CorporationInventors: Tsuyoshi Kawakami, Yoshiyuki Nakaki, Yoshio Fujii, Hiroshi Watanabe, Shuhei Nakata, Kohei Ebihara, Akihiko Furukawa
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Patent number: 8723259Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: GrantFiled: February 23, 2010Date of Patent: May 13, 2014Assignee: Mitsubishi Electric CorporationInventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura