Patents by Inventor Shuhei Yoshitomi

Shuhei Yoshitomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150099179
    Abstract: To increase the volume density or weight density of lithium ions that can be received and released in and from a positive electrode active material to achieve high capacity and high energy density of a secondary battery. A lithium manganese composite oxide represented by LixMnyMzOw that includes a region belonging to a space group C2/c and is covered with a carbon-containing layer is used as the positive electrode active material. The element M is an element other than lithium and manganese. The lithium manganese composite oxide has high structural stability and high capacity.
    Type: Application
    Filed: September 26, 2014
    Publication date: April 9, 2015
    Inventors: Tatsuya IKENUMA, Shuhei YOSHITOMI, Takahiro KAWAKAMI, Yumiko YONEDA (Former family: SAITO), Yohei MOMMA
  • Publication number: 20150087091
    Abstract: Provided is a test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test. Provided is to detect a transistor whose reliability is high in a shorter period of time than a BT test and manufacture an electronic device with high reliability efficiently. Hysteresis characteristics revealed in the result of the Vg-Id measurement with light irradiation to the transistor correlate with the result of a BT test; whether the reliability of the transistor is Good or Not-Good can be judged. Accordingly, the test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test can be provided.
    Type: Application
    Filed: December 2, 2014
    Publication date: March 26, 2015
    Inventors: Hiromichi GODO, Shuhei YOSHITOMI
  • Publication number: 20150069393
    Abstract: Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: ?1 and ?2, ?1<?2 is satisfied, and ?2 is 300 seconds or less. In addition, a semiconductor device including the transistor is manufactured.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 12, 2015
    Inventors: Masashi TSUBUKU, Takayuki INOUE, Suzunosuke HIRAISHI, Erumu KIKUCHI, Hiromichi GODO, Shuhei YOSHITOMI, Koki INOUE, Akiharu MIYANAGA, Shunpei YAMAZAKI
  • Publication number: 20150044818
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Application
    Filed: October 23, 2014
    Publication date: February 12, 2015
    Inventors: Masashi TSUBUKU, Shuhei YOSHITOMI, Takahiro TSUJI, Miyuki HOSOBA, Junichiro SAKATA, Hiroyuki TOMATSU, Masahiko HAYAKAWA
  • Publication number: 20150014581
    Abstract: A positive electrode active material that achieves high capacity and high energy density of a secondary battery is provided. The positive electrode active material is represented by Li2Mn1-XAXO3 and contains a metal element, Si, or P as A. The positive electrode active material has higher discharge capacity than Li2MnO3.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 15, 2015
    Inventors: Takahiro KAWAKAMI, Shuhei YOSHITOMI, Teruaki OCHIAI, Yumiko SAITO, Yohei MOMMA, Satoshi SEO
  • Publication number: 20150014605
    Abstract: The amount of lithium ions that can be received and released in and from a positive electrode active material is increased, and high capacity and high energy density of a secondary battery are achieved. Provided is a lithium-manganese composite oxide represented by LixMnyMzOw, where M is a metal element other than Li and Mn, or Si or P, and y, z, and w satisfy 0?x/(y+z)<2, y>0, z>0, 0.26?(y+z)/w<0.5, and 0.2<z/y<1.2. The lithium manganese composite oxide has high structural stability and high capacity.
    Type: Application
    Filed: June 30, 2014
    Publication date: January 15, 2015
    Inventors: Takahiro KAWAKAMI, Shuhei YOSHITOMI, Teruaki OCHIAI, Yumiko SAITO, Yohei MOMMA, Satoshi SEO, Mayumi MIKAMI, Shunsuke ADACHI
  • Patent number: 8912016
    Abstract: Provided is a test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test. Provided is to detect a transistor whose reliability is high in a shorter period of time than a BT test and manufacture an electronic device with high reliability efficiently. Hysteresis characteristics revealed in the result of the Vg-Id measurement with light irradiation to the transistor correlate with the result of a BT test; whether the reliability of the transistor is Good or Not-Good can be judged. Accordingly, the test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test can be provided.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Shuhei Yoshitomi
  • Patent number: 8895976
    Abstract: Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: ?1 and ?2, ?1<?2 is satisfied, and ?2 is 300 seconds or less. In addition, a semiconductor device including the transistor is manufactured.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Takayuki Inoue, Suzunosuke Hiraishi, Erumu Kikuchi, Hiromichi Godo, Shuhei Yoshitomi, Koki Inoue, Akiharu Miyanaga, Shunpei Yamazaki
  • Patent number: 8889496
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Shuhei Yoshitomi, Takahiro Tsuji, Miyuki Hosoba, Junichiro Sakata, Hiroyuki Tomatsu, Masahiko Hayakawa
  • Publication number: 20140332715
    Abstract: To increase the amount of lithium ions that can be received and released in and from a positive electrode active material to achieve high capacity and high energy density of a secondary battery. A composite material of crystallites of LiMn2O4 (crystallites with a spinel crystal structure) and crystallites of Li2MnO3 (crystallites with a layered rock-salt crystal structure) is used as a positive electrode active material. The lithium manganese oxide composite has high structural stability and high capacity.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 13, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takahiro KAWAKAMI, Shuhei Yoshitomi, Teruaki Ochiai, Satoshi Seo, Yohei Momma, Yumiko Saito
  • Patent number: 8821601
    Abstract: A hydrogen generating element which can supply hydrogen efficiently and stably, is safe, and has low environmental load is provided. Further, a hydrogen generation device to which the hydrogen generating element is applied is provided. Furthermore, a power generation device and a driving device to each of which the hydrogen generation device is applied are provided. A hydrogen generating element in which a needle-like or dome-like silicon microstructure is formed over a base may be used and reacted with water, whereby hydrogen is efficiently generated. The hydrogen generating element may be applied to a hydrogen generation device. The hydrogen generation device may be applied to a power generation device and a driving device.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomokazu Yokoi, Shuhei Yoshitomi, Kensuke Yoshizumi
  • Publication number: 20130280857
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Application
    Filed: June 13, 2013
    Publication date: October 24, 2013
    Inventors: Masashi TSUBUKU, Shuhei YOSHITOMI, Takahiro TUJI, Miyuki HOSOBA, Junichiro SAKATA, Hiroyuki TOMATSU, Masahiko HAYAKAWA
  • Patent number: 8466014
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: June 18, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Shuhei Yoshitomi, Takahiro Tuji, Miyuki Hosoba, Junichiro Sakata, Hiroyuki Tomatsu, Masahiko Hayakawa
  • Publication number: 20120289008
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Application
    Filed: July 26, 2012
    Publication date: November 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masashi TSUBUKU, Shuhei YOSHITOMI, Takahiro TUJI, Miyuki HOSOBA, Junichiro SAKATA, Hiroyuki TOMATSU, Masahiko HAYAKAWA
  • Patent number: 8268642
    Abstract: An object is to suppress a significant change in electrical characteristics of thin film transistors and a deviation thereof from the designed range due to static electricity, and to improve the yield in manufacturing semiconductor devices. In order to prevent a substrate from being charged with static electricity by heat treatment or to favorably reduce static electricity with which a substrate is charged in a manufacturing process of a semiconductor device, heat treatment is performed with a substrate provided with a thin film transistor stored in a conductive container. In addition, a heating apparatus for performing the heat treatment is electrically connected to a ground potential, and the container and the substrate are also electrically connected to the ground potential.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: September 18, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shuhei Yoshitomi, Masashi Tsubuku, Shunpei Yamazaki
  • Patent number: 8236627
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Shuhei Yoshitomi, Takahiro Tuji, Miyuki Hosoba, Junichiro Sakata, Hiroyuki Tomatsu, Masahiko Hayakawa
  • Publication number: 20120189929
    Abstract: A hydrogen generating element which can supply hydrogen efficiently and stably, is safe, and has low environmental load is provided. Further, a hydrogen generation device to which the hydrogen generating element is applied is provided. Furthermore, a power generation device and a driving device to each of which the hydrogen generation device is applied are provided. A hydrogen generating element in which a needle-like or dome-like silicon microstructure is formed over a base may be used and reacted with water, whereby hydrogen is efficiently generated. The hydrogen generating element may be applied to a hydrogen generation device. The hydrogen generation device may be applied to a power generation device and a driving device.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 26, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tomokazu YOKOI, Shuhei Yoshitomi, Kensuke Yoshizumi
  • Publication number: 20110315979
    Abstract: Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: ?1 and ?2, ?1<?2 is satisfied, and ?2 is 300 seconds or less. In addition, a semiconductor device including the transistor is manufactured.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 29, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masashi Tsubuku, Takayuki Inoue, Suzunosuke Hiraishi, Erumu Kikuchi, Hiromichi Godo, Shuhei Yoshitomi, Koki Inoue, Akiharu Miyanaga, Shunpei Yamazaki
  • Publication number: 20110318851
    Abstract: Provided is a test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test. Provided is to detect a transistor whose reliability is high in a shorter period of time than a BT test and manufacture an electronic device with high reliability efficiently. Hysteresis characteristics revealed in the result of the Vg-Id measurement with light irradiation to the transistor correlate with the result of a BT test; whether the reliability of the transistor is Good or Not-Good can be judged. Accordingly, the test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test can be provided.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 29, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hiromichi GODO, Shuhei YOSHITOMI
  • Publication number: 20110081747
    Abstract: An object is to suppress a significant change in electrical characteristics of thin film transistors and a deviation thereof from the designed range due to static electricity, and to improve the yield in manufacturing semiconductor devices. In order to prevent a substrate from being charged with static electricity by heat treatment or to favorably reduce static electricity with which a substrate is charged in a manufacturing process of a semiconductor device, heat treatment is performed with a substrate provided with a thin film transistor stored in a conductive container. In addition, a heating apparatus for performing the heat treatment is electrically connected to a ground potential, and the container and the substrate are also electrically connected to the ground potential.
    Type: Application
    Filed: September 29, 2010
    Publication date: April 7, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shuhei Yoshitomi, Masashi Tsubuku, Shunpei Yamazaki