Patents by Inventor Shuichi Matsuda
Shuichi Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6339337Abstract: An infrared ray test for a semiconductor chip is conducted by irradiating infrared ray onto a bottom surface of a semiconductor chip, receiving the infrared ray reflected from a bonding pad and displaying the image of the bonding pad on a monitor. The image obtained from the infrared ray has information whether the bonding pad itself or a portion of the silicon substrate underlying the bonding pad has a defect or whether or not there is a deviation of the bonding pad with respect to the bump.Type: GrantFiled: March 26, 1998Date of Patent: January 15, 2002Assignee: NEC CorporationInventors: Shuichi Matsuda, Keiichiro Kata, Ryoji Sato, Masaharu Sato
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Publication number: 20020000654Abstract: A semiconductor device equipped with a TAB (tape automated bonding) tape. A desired pattern of wiring is formed on one surface of the TAB tape and a semiconductor chip having tow or more chip electrodes is disposed on the other surface of the TAB tape. The wiring and the chip electrodes are electrically interconnected via bumps that are formed in through-holes of the wiring in confronting relationship with the chip electrodes. This prevents fault connection between the chip electrodes and the bumps.Type: ApplicationFiled: December 28, 1998Publication date: January 3, 2002Inventor: SHUICHI MATSUDA
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Patent number: 5905303Abstract: An insulating film has conductive layers on a first surface and conductive protrusions on a second surface. The conductive layers are connected to the conductive protrusions via through holes provided in the insulating film. A semiconductor chip having pads is adhered by an adhesive layer to the insulating film. Then, the conductive layers are locally pressured, so that the conductive layers are electrically connected to respective ones of the pads.Type: GrantFiled: June 12, 1997Date of Patent: May 18, 1999Assignee: NEC CorporationInventors: Keiichiro Kata, Shuichi Matsuda, Eiji Hagimoto
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Patent number: 5897337Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor chip and a carrier film which includes an insulating film and wiring patterns formed on one of main surfaces of the insulating film, an adhesive layer is formed on a surface of a semiconductor wafer having a number of integrated circuits. Each of the integrated circuits has electrode pads for external connection on the foregoing surface of the semiconductor wafer. Subsequently, openings are formed at regions of the adhesive layer corresponding to the electrode pads, and then, the semiconductor wafer is cut per integrated circuit so as to obtain the semiconductor chips. Thereafter, the electrode pads of the semiconductor chip and the wiring patterns of the carrier film are connected to each other through the corresponding openings of the adhesive layer, respectively. Then, the semiconductor chip and the carrier film are bonded together via the adhesive layer interposed therebetween.Type: GrantFiled: September 25, 1995Date of Patent: April 27, 1999Assignee: NEC CorporationInventors: Keiichiro Kata, Shuichi Matsuda
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Patent number: 5759873Abstract: In a method of manufacturing a chip size semiconductor device comprising a semiconductor chip and a carrier tape including an insulating film and wiring patterns formed on one surface of the insulating film, the method comprises the steps of bonding the semiconductor chip and the carrier tape by the use of an adhesive film having a predetermined size corresponding to an adhesive area of the semiconductor chip. The step of bonding comprises the substeps of cutting away the adhesive film by punching from an adhesive film tape held above the semiconductor chip mounted on a table and subsequently setting the adhesive film on the adhesive area by moving the adhesive film downwardly.Type: GrantFiled: October 17, 1996Date of Patent: June 2, 1998Assignee: NEC CorporationInventors: Keiichiro Kata, Shuichi Matsuda, Hironori Ono
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Patent number: 5757068Abstract: There is provided a carrier film (130, 140) having a plurality of slits (135) formed by the periphery of a chip mounting region (138) on which a semiconductor chip 10 is to be mounted. The chip mounting region is rectangular and four slits are formed along the four sides of the chip mounting region. The slits may be formed by means of punching with a die or etching.Type: GrantFiled: September 25, 1995Date of Patent: May 26, 1998Assignee: NEC CorporationInventors: Keiichiro Kata, Shuichi Matsuda
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Patent number: 5757078Abstract: A semiconductor device including a semiconductor chip having electrode pads, a package composed of a plurality of insulating films and adhered to the semiconductor chip by an adhesive agent. The package includes wiring patterns interposed between the plurality of insulating films, and the wiring patterns are selectively connected to the electrode pads at one end, and to the plurality of electrically conductive protrusions at the other end, via viaholes. The semiconductor device further includes a plurality of electrically conductive protrusions extending from the outermost wiring patterns via the viaholes provided in the outermost insulating film.Type: GrantFiled: April 24, 1996Date of Patent: May 26, 1998Assignee: NEC CorporationInventors: Shuichi Matsuda, Kazutaka Shoji
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Patent number: 5726489Abstract: A film carrier semiconductor device 10 comprises a semiconductor bare chip 20 and a carrier film 30. Chip electrodes 21 are provided on the bare chip 20. Each chip electrode 21 is electrically connected to the carrier film 30. Bump electrodes 37 are formed and arranged as an array on the carrier film 30 on the side of the other surface 31b of the film 30. Interconnection layers 32 are provided on the carrier film 30 to connect some of the chip electrodes 21b to the bump electrodes 37a and 37b. The semiconductor device 10 also comprises a noise blocking layer 60 provided on the carrier film 30 outside the chip mounting region. The noise blocking layer 60 is electrically connected to at least one of the chip electrodes 21a.Type: GrantFiled: September 20, 1995Date of Patent: March 10, 1998Assignee: NEC CorporationInventors: Shuichi Matsuda, Keiichiro Kata
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Patent number: 5683942Abstract: An insulating film has conductive layers on a first surface and conductive protrusions on a second surface. The conductive layers are connected to the conductive protrusions via through holes provided in the insulating film. A semiconductor chip having pads is adhered by an adhesive layer to the insulating film. Then, the conductive layers are locally pressured, so that the conductive layers are electrically connected to respective ones of the pads.Type: GrantFiled: May 25, 1995Date of Patent: November 4, 1997Assignee: NEC CorporationInventors: Keiichiro Kata, Shuichi Matsuda, Eiji Hagimoto
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Patent number: 5424932Abstract: A switching power supply wherein high speed switching and high output voltages are obtained by utilizing an auxiliary power supply and a synchronizing signal having a sawtooth shaped waveform, whereby delay time in a control signal to an FET switch is substantially reduced. The switching power supply comprises a secondary output circuit which is supplied with a square waveform voltage and utilizes an FET switch which controls the width of pulses chopped from the square waveform voltage and causes the output circuit to produce a direct current output voltage having a set value. The control signal to the FET switch is produced by a control circuit which is independently powered by the auxiliary power supply and supplied with the synchronizing signal.Type: GrantFiled: March 25, 1993Date of Patent: June 13, 1995Assignee: Yokogawa Electric CorporationInventors: Kiyoharu Inou, Shuichi Matsuda
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Patent number: 5322748Abstract: A photomask includes a transparent substrate, a light shielding film formed on the substrate, and a transparent film formed on the light shielding film and the substrate. The light shielding film has a bottom in contact with the substrate, a side face at an acute angle to the bottom, and an upper face in parallel with the bottom and at an obtuse angle to the side face. According to the light shielding film having such a configuration, a phase shift portion of a predetermined width and thickness can be formed accurately in the periphery of the light shielding film. The inferior influence of reflecting light with respect to the pattern resolution can be reduced if films of low reflectance are provided in the upper and lower portions of the light shielding film to improve the pattern resolution.Type: GrantFiled: August 21, 1992Date of Patent: June 21, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yaichiro Watakabe, Shuichi Matsuda
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Patent number: 4985319Abstract: A photomask manufacturing process including a step of forming metal silicide film on a transparent silica glass substrate. A resist is applied onto the metal silicide film and then a patterning mask is provided by light or electron beam, followed by developing step. Exposed portions of the metal silicide film is etched away using a dry etching process.Type: GrantFiled: October 23, 1989Date of Patent: January 15, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yaichiro Watakabe, Tatsuo Okamoto, Shuichi Matsuda
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Patent number: 4957834Abstract: In manufacturing a photomask, a molybdenum silicide film is formed on the main surface of a quartz substrate. A resist film having a pattern is, then, formed on the molybdenum silicide film. Thereafter, the molybdenum silicide film is etched using the resist film as a mask. The etching is effected in a plasma generated in a mixed gas containing nitrogen gas in CF.sub.4 gas.Type: GrantFiled: November 3, 1988Date of Patent: September 18, 1990Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shuichi Matsuda, Yaichiro Watakabe
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Patent number: 4876164Abstract: A photomask manufacturing process including a step of forming metal silicide film on a transparent silica glass substrate. A resist is applied onto the metal silicide film and then a patterning mask is provided by light or electron beam, followed by developing step. Exposed portions of the metal silicide film is etched away using a dry etching process.Type: GrantFiled: July 17, 1987Date of Patent: October 24, 1989Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yaichiro Watakabe, Tatsuo Okamoto, Shuichi Matsuda
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Patent number: 4792461Abstract: A silicide film of oxidized transition metal 3 formed on a transparent substrate 1 has a low reflectance and in consequence, a high resolution can be obtained and dry etching thereof can be easily done. In addition, since said silicide film 3 has good adhesion to a transparent substrate 1, file patterns therein do not peel off at the time of rinsing the mask.Type: GrantFiled: June 22, 1987Date of Patent: December 20, 1988Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yaichiro Watakabe, Shuichi Matsuda
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Patent number: 4783371Abstract: A silicide film of oxidized transition metal 3 formed on a transparent substrate 1 has a low reflectance and in consequence, a high resolution can be obtained and dry etching thereof can be easily done. In addition, since said silicide film 3 has good adhesion to a transparent substrate 1, fine patterns therein do not peel off at the time of rinsing the mask.Type: GrantFiled: March 6, 1986Date of Patent: November 8, 1988Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yaichiro Watakabe, Shuichi Matsuda
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Patent number: 4738907Abstract: A photomask manufacturing process including step of forming on a transparent silica glass substrate a silicide film in which an alloy comprising two or more metal elements is silicidized. A resist is applied onto the silicide film and then a patterning mask is provided by light or electron beam, followed by developing step. Exposed portion of the silicide film is etched away using a dry etching process.Type: GrantFiled: March 20, 1986Date of Patent: April 19, 1988Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akira Shigetomi, Shuichi Matsuda
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Patent number: 4717625Abstract: A transition metal silicide film 3 is formed on a transparent substrate 1, and an oxidized transition metal silicide film 4 is formed on said transition metal silicide film 3. Dry etching can be easily applied to the transition metal silicide film 3 and the oxidized transition metal silicide film 4. Since the silicified metal films have good adhesion to the transparent substrate 1, the fine patterns can hardly be detached at the time of mask rinsing. In addition, the oxidized transition metal silicide film 4 has a low reflection factor, which prevents the lowering of the resolution.Type: GrantFiled: March 6, 1986Date of Patent: January 5, 1988Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yaichiro Watakabe, Shuichi Matsuda
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Patent number: 4661426Abstract: A metal silicide photomask manufacturing process including a step of forming metal silicide film on a transparent silica glass substrate. A resist is applied onto the metal silicide film and then a patterning mask is drawn by using light or electron beam, followed by developing step, so that some portion of the applied resist can be removed wherein the metal silicide is exposed. Scum is removed by oxygen plasma etching process, thereby to form an oxide film on an exposed portion of the metal silicide. The left resist portion and the portion of the metal silicide film laying under the resist portion is etched away using a dry etching process in which the oxide film serves as a mask.Type: GrantFiled: March 31, 1986Date of Patent: April 28, 1987Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shuichi Matsuda, Akira Shigetomi