Abstract: The processor according to the present invention includes a flag register that stores a first flag group and a second flag group. The second flag group includes the same operation flags (a carry flag and an overflow flag) as the first flag group. The processor executes first-type instructions and second-type instructions. The first-type instruction instructs to perform an operation and to update the first flag group according to the result of the operation. The second-type instruction instructs to perform an operation different from the operation in the first-type instruction and updates the second flag group according to the result of the operation.

Abstract: A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in

Abstract: An instruction conversion apparatus and method for converting instruction sequences not including conditional instructions into instruction sequences including conditional instructions wherein the conditional instructions include both a condition and an operation code for execution by the processor when the condition is satisfied. An obtaining unit receives an instruction sequence that does not include a conditional instruction whereby an instruction sequence detection unit detects a conversion target instruction sequence which transfers different transfer objects to the same storage resource when a predetermined condition is satisfied. A judging unit judges whether the instruction set of a specialized processor is assigned a conditional instruction including the same condition as the precondition whereby a conversion unit can then convert the conversion target instruction sequence into the instruction sequence including a conditional instruction with the predetermined condition.

Abstract: A processor includes a constant register 36 for storing a constant, a format decoder 21 for decoding a format code located in the P0.0 field of an instruction stored in the instruction register 10, and a constant register control unit 32 which, when the format decoder 21 has decoded that the instruction includes a constant to be stored in the constant register 36, shifts the presently stored value in the constant register 36 and stores the constant into the constant register 36.

Abstract: When a subroutine call instruction is transferred from the instruction memory 39 to the IDB 29 and decoded by the decoder 18, the following operations (1)-(3) are executed in parallel: (1) a return address storage operation for incrementing the value stored in the PC 15 using the INC 16 and for storing the incremented value in the LR 13 as a return address; (2) a branch operation for storing the entry address of the subroutine included in the subroutine call instruction in the PC 15; and (3) a stack reserve operation for preparing for the following use of a stack area by adding a value “−4” to the value stored in the SP 12 using the adder 22 and for storing the addition result in the SP 12.

Abstract: A processor for executing operations based on instructions includes an operation constant register 361, a branching constant register 362, a decoding unit 20 for decoding an instruction stored in an instruction register 10, a constant register control unit 32, and an execution unit 30. When the decoding unit 20 finds that the instruction includes a constant to be stored in the branching constant register 362, the constant register control unit 32 shifts a present value in the branching constant register 362 and inserts the constant to be stored, thereby storing a new constant in the branching constant register 362. When the decoding unit 20 finds that a constant is to be stored in the operation constant register 361, the constant register control unit 32 shifts the present value in the operation constant register 361 and inserts the constant to be stored, thereby storing a new constant in the operation constant register 361.

Abstract: A processor for decoding and executing an instruction includes: an instruction register 10 for storing an instruction; a format decoder 21 for decoding a format code located in the P0.0 field 11 of the instruction stored in the instruction register 10; a constant storage unit including a storage region; a constant register control unit 32 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes a constant to be stored in the constant register 36, transfers the constant from the instruction register 10 to the constant storage unit 36; and a constant register output unit 41 which, when the format decoder 21 has referred to the format code and decoded that an operation field includes an operation code showing an operation that should be executed and a piece of an operand that should be used for the operation, links the constant stored in the constant register 36 with the piece of the operand.

Abstract: A processor detects a function which includes no function call instruction and no update of the return address /calculation register from an assembler program. After the detection, the processor outputs a special return address to the end of the function detected, and executes the assembler program. The processor stores a return address not only on the stack but in the return address/calculation register. When the special return instruction has been fetched, the return address is moved from the return address/calculation register without accessing to the stack.

Abstract: On receiving a target address specification from a programmer, an execution code reconversion unit reconverts an operation code of an execution code loaded in the specified address to a mnemonic code. When the execution code includes a subconstant as an operand, a constant restoration unit detects constant division information that shows the subconstant included in the execution code in a debug information storage unit, in order to specify the long-word constant from which the subconstant has been generated. The constant restoration unit then replaces the subconstant with the long-word constant. As a result, the mnemonic code is displayed with the long-word constant.

Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code "cc" that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant "const". The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

Abstract: A program translating apparatus is composed of a translation unit 103 and a link unit 108. The translation unit 103 includes a determination unit 105 which detects the stack size to be needed for each subroutine included in a source program to be translated into a machine instruction sequence and the name of a register to be retrieved in the process of each subroutine. The determination unit 105 then stores the stack size and the name detected into a file together with the machine instruction sequence. The link unit 108 includes the following units: A branch instruction detection unit 109 detects a branch instruction from the machine instruction sequence when machine instruction sequences stored in different files are linked each other. A file detection unit 110 and an acquisition unit 111 retrieve the stack size and the register name from the file which has the branch target subroutine.

Abstract: A branch instruction includes a set of branch prediction information 13b and a set of branch history information 13c. The set of branch prediction information 13b is made up of 1 bit which predicts whether a branch will be performed during the next execution of the instruction. The set of branch history information 13c is made up of 2 bits showing a frequency, with which the branch has been taken, is "very high", "high", "low" or "very low". An instruction fetching unit 12 prefetches an instruction from a cache memory 11a in accordance with the set of branch prediction information 13b. After an instruction executing unit 15 completes an execution of the branch instruction, a branch history information generating unit 16 generates a new set of branch history information and a branch prediction information generating unit 17 generates a new set of branch prediction information, in accordance with the execution result and the preceding branch history information 13c.

Abstract: A program development system in which the debugging apparatus is informed of all of the optimization processes which have been performed. A primitive storage unit stores record information for the optimization processes. The input unit receives an input of a variable and a value, or an input of a line where execution is to be halted. The primitive combining unit obtains record information showing the optimization processes. The code execution unit executes the execution code. The variable operation unit obtains the value of a variable based on relations between variables and resources. The output unit displays the obtained value of the variable. The line display unit displays the program or the generated execution code. The line information display unit displays, in line units, information relating to the optimization performed for each line, The operation-possible variable display unit displays, for each line, variables which can be set and referred to in the line.

Abstract: A surgical manipulator system comprising at least one surgical manipulator, at least one guide, a detector, and a drive controller. The surgical manipulator has a surgical device for performing a desired operation. The guide guides the surgical device. The detector detects a position and/or orientation relationship between the surgical device and the guide, and/or a position and/or orientation relationship between the surgical device and another surgical device. The drive controller controls the surgical manipulator such that the surgical device is guided by the guide.

Abstract: A compiler comprises a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before the entry of a loop, generating second loop exclusive instructions, and placing the instruction at each place to branch to the entry of the loop.

Abstract: An information processing apparatus for executing a program, the apparatus including: a register set made up of a plurality of registers; a decoding unit for decoding machine language instructions in the program and extracting a selected instruction which indicates data transfer between a plurality of registers designated by a first operand, which is made up of a single field of at least one bit which shows whether an individual register out of the register set is designated and a group field which shows whether a plurality of other registers out of the register set are designated as a group, and consecutive addresses of memory designated by a second operand as an effective address of memory; a determining unit for determining whether each bit in the single field and group field of the first operand of the extracted machine language instruction is valid; a first generating unit for generating a register number for a register corresponding to a bit determined as being valid in the single field, a second genera

Abstract: Regioselective acetylation of the 9-hydroxyl group on N-acetylneuraminic acid is achieved enzymatically for producing oligosaccharides which contain a terminal N-acetylneuraminic acid moiety. This method provides access to O-acylated disialogangliosides as well as other N-acetyl-neuraminic acid oligosaccharides. These compounds are biologically and medicinally important and are difficult to obtain from nature or by chemical acylations. The methodology affords simple reaction conditions and minimal purification steps. In addition, the process affords good yields and the enzymes and reagents employed are commercially available with high stability and low costs.

Abstract: A program translating apparatus is composed of a translation unit 103 and a link unit 108. The translation unit 103 includes a determination unit 105 which detects the stack size to be needed for each subroutine included in a source program to be translated into a machine instruction sequence and the name of a register to be retrieved in the process of each subroutine. The determination unit 105 then stores the stack size and the name detected into a file together with the machine instruction sequence. The link unit 108 includes the following units: A branch instruction detection unit 109 detects a branch instruction from the machine instruction sequence when machine instruction sequences stored in different files are linked each other. A file detection unit 110 and an acquisition unit 111 retrieve the stack size and the register name from the file which has the branch target subroutine.

Abstract: A multi-degree-of-freedom manipulator includes a flexible tube having a plurality of flex portions provided therealong, a plurality of actuators made of shape memory alloy and respectively provided near the flex portions to correspond to the flex portions, for flexing the flex portions, two common energy transmission paths, extending along the flexible tube, for transmitting an energy to the actuators, and selective energy supply members, provided between the common energy transmission paths and the actuators in series, for controlling the energy supplied from the common energy transmission path to the actuators, thereby respectively independently driving the actuators to bend the flexible tube.

Abstract: A multi-degree-of-freedom manipulator includes a flexible tube having a plurality of flex portions provided therealong, a plurality of actuators made of shape memory alloy and respectively provided near the flex portions to correspond to the flex portions, for flexing the flex portions, two common energy transmission paths, extending along the flexible tube, for transmitting an energy to the actuators, and selective energy supply members, provided between the common energy transmission paths and the actuators in series, for controlling the energy supplied from the common energy transmission path to the actuators, thereby respectively independently driving the actuators to bend the flexible tube.