Patents by Inventor Shuichi Yagi
Shuichi Yagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120404Abstract: This normally-off mode polarization super junction GaN-based field effect transistor has an undoped GaN layer 11, an AlxGa1-xN layer 12 (0<x<1), an island-like undoped GaN layer 13, a p-type GaN layer 14, a p-type InyGa1-yN layer 15 (0<y<1), a gate electrode 16 on the p-type InyGa1-yN layer 15 and a source electrode 17 and a drain electrode 17 on the AlxGa1-xN layer 12. When the polarization charge amount of the hetero-interface between the AlxGa1-xN layer 12 and the undoped GaN layer 11 and the hetero-interface between the AlxGa1-xN layer 12 and the undoped GaN layer 13 is denoted as NPZ and the thickness of the AlxGa1-xN layer 12 is denoted as d, NPZ d?2.64×1014 [cm?2 nm] is satisfied.Type: ApplicationFiled: October 5, 2021Publication date: April 11, 2024Inventors: Hiroji KAWAI, Shuichi YAGI, Hironobu NARUI
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Publication number: 20230352573Abstract: A semiconductor element includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first intermediate layer, a second intermediate layer, a source electrode, a drain electrode, and a gate electrode. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The band gaps of the first intermediate layer and the second intermediate layer that sandwich the second semiconductor layer are larger than the band gap of the second semiconductor layer.Type: ApplicationFiled: July 6, 2023Publication date: November 2, 2023Inventors: Hisao SATO, Koji OKUNO, Daisuke SHINODA, Toshiya UEMURA, Hironobu NARUI, Hiroji KAWAI, Shuichi YAGI
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Publication number: 20230170407Abstract: This normally-off mode polarization super junction GaN-based FET has an undoped GaN layer 11, an AlxGa1-xN layer 12, an island-like undoped GaN layer 13, a p-type GaN layer 14 and a p-type InyGa1-yN layer 15 which are stacked in order. The FET has a gate electrode 16 on the uppermost layer, a source electrode 17 and a drain electrode 17 on the AlxGa1-xN layer 12 and a p-type InzGa1-zN layer 19 and a gate electrode 20 which are located beside one end of the undoped GaN layer 13 on the AlxGa1-xN layer 12. The gate electrode 20 may be provided on the p-type InzGa1-zN layer 19 via a gate insulating film.Type: ApplicationFiled: September 16, 2021Publication date: June 1, 2023Inventors: Hiroji KAWAI, Shuichi YAGI, Hironobu NARUI
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Publication number: 20220238728Abstract: This diode is configured by a double gate PSJ-GaN-based FET. This FET has a GaN layer 11, an AlxGa1-xN layer 12, an undoped GaN layer 13, and a p-type GaN layer 14. A source electrode 19 and a drain electrode 20 are provided on the AlxGa1-xN layer 12, a first gate electrode 15 is provided on the p-type GaN layer 14, and a second gate electrode 18 is provided on a gate insulating film 17 provided inside a groove 16 which is provided in the AlxGa1-xN layer 12 between the source electrode 19 and the undoped GaN layer 13. The source electrode 19, the first gate electrode 15, and the second gate electrode 18 are connected to each other. Or the source electrode 19 and the second gate electrode 18 are connected to each other, and a positive voltage is applied to the first gate electrode 15 for the source electrode 19 and the second gate el electrode 18.Type: ApplicationFiled: March 5, 2020Publication date: July 28, 2022Inventors: Hiroji KAWAI, Shuichi YAGI, Takeru SAITO, Fumihiko NAKAMURA, Hironobu NARUI
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Patent number: 9991335Abstract: Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped AlxGa1-xN layer 12 with a thickness not smaller than 25 nm and not larger than 47 nm and 0.17?x?0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10?18) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w [cm?3] of the p-type GaN layer 14, tR?0.864/(x?0.134)+46.0 [nm] is satisfied.Type: GrantFiled: November 18, 2014Date of Patent: June 5, 2018Assignee: POWDEC K.K.Inventors: Shoko Echigoya, Fumihiko Nakamura, Shuichi Yagi, Souta Matsumoto, Hiroji Kawai
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Publication number: 20170263710Abstract: Provided is a semiconductor element in which a two-dimensional hole gas with an enough concentration can exist, even though the p-type GaN layer is not provided on the topmost surface of the polarization super junction region. The semiconductor element comprises a polarization super junction region comprising an undoped GaN layer 11 with a thickness a [nm] (a is not smaller than 10 nm and not larger than 1000 nm), an AlxGa1-xN layer 12 and an undoped GaN layer 13. The Al composition x and the thickness t [nm] of the AlxGa1-xN layer 12 satisfy the following equation t??(a)x?(a) Where ? is expressed as Log (?)=p0+p1 log (a)+p2{log (a)}2 (p0=7.3295, p1=?3.5599, p2=0.6912) and ? is expressed as ?=p?0+p?1 log (a)+p?2{log (a)}2 (p?0=?3.6509, p?1=1.9445, p?2=?0.3793).Type: ApplicationFiled: November 5, 2015Publication date: September 14, 2017Applicant: POWDEC K.K.Inventors: Souta MATSUMOTO, Shoko ECHIGOYA, Shuichi YAGI, Fumihiko NAKAMURA, Hiroji KAWAI
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Publication number: 20160093691Abstract: Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped AlxGa1-xN layer 12 with a thickness not smaller than 25 nm and not larger than 47 nm and 0.17?x?0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10?18) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w [cm?3] of the p-type GaN layer 14, tR?0.864/(x?0.134)+46.0 [nm] is satisfied.Type: ApplicationFiled: November 18, 2014Publication date: March 31, 2016Inventors: Shoko ECHIGOYA, Fumihiko NAKAMURA, Shuichi YAGI, Souta MATSUMOTO, Hiroji KAWAI
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Patent number: 8543701Abstract: It is an object of this invention to provide a computer system and its control method capable of preventing allocation of a resource(s), which is not intended by a superior administrator, to a certain storage administrator even when the superior administrator sets a certain authority to that storage administrator and intends to allocate a resource(s), which is required to enable this authority, to the storage administrator. When the superior administrator sets a certain authority to a certain storage administrator and intends to allocate a resource(s), which is required to enable this authority, to the storage administrator, the computer system prevents allocation of a resource(s), which is not intended by the superior administrator, to that storage administrator by optimizing allocation of resource groups and authorities to the storage administrator.Type: GrantFiled: May 23, 2011Date of Patent: September 24, 2013Assignee: Hitachi, Ltd.Inventors: Keisuke Tominaga, Shuichi Yagi, Nobuyuki Osaki
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Patent number: 8423796Abstract: A storage device and a data processing method of the storage device are provided which can prevent leaking of data attributed to stealing or taking out of a disk device. The storage device includes: disk adapters, each connected to HDDs which constitute one or more RAID groups; and a management part which manages a storage area provided by the HDDs in a state that the storage area is divided into logical storage areas, and manages the RAID groups. The management part sets an encryption state indicative of whether or not the data is to be encrypted with respect to the RAID groups when all of the disk adapters are connected to the HDDs which belong to the RAID groups are encryption adapters. The management part also encrypts, based on the encryption state set with respect to the RAID groups, and stores the encrypted data in the HDD.Type: GrantFiled: September 22, 2008Date of Patent: April 16, 2013Assignee: Hitachi, Ltd.Inventors: Shin Nishihara, Shuichi Yagi, Yasuyuki Nagasoe
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Publication number: 20120304189Abstract: It is an object of this invention to provide a computer system and its control method capable of preventing allocation of a resource(s), which is not intended by a superior administrator, to a certain storage administrator even when the superior administrator sets a certain authority to that storage administrator and intends to allocate a resource(s), which is required to enable this authority, to the storage administrator. When the superior administrator sets a certain authority to a certain storage administrator and intends to allocate a resource(s), which is required to enable this authority, to the storage administrator, the computer system prevents allocation of a resource(s), which is not intended by the superior administrator, to that storage administrator by optimizing allocation of resource groups and authorities to the storage administrator.Type: ApplicationFiled: May 23, 2011Publication date: November 29, 2012Applicant: HITACHI, LTD.Inventors: Keisuke Tominaga, Shuichi Yagi, Nobuyuki Osaki
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Publication number: 20120280363Abstract: The method for manufacturing a semiconductor device comprises steps of: forming a growth mask with a plurality of openings directly or indirectly upon a substrate that comprises a material differing from GaN-based semiconductor; and growing a plurality of island-like GaN-based semiconductor layers upon the substrate using the growth mask in the (0001) plane orientation in a manner such that the 1-100 direction extends in a direction parallel to the striped openings of the growth mask.Type: ApplicationFiled: August 17, 2010Publication date: November 8, 2012Applicant: POWDEC K. K.Inventors: Yasunobu Sumida, Shoko Hirata, Takayuki Inada, Shuichi Yagi, Hiroji Kawai
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Patent number: 8209495Abstract: There is provided a storage management system capable of utilizing division management with enhanced flexibility and of enhancing security of the entire system, by providing functions by program products in each division unit of a storage subsystem. The storage management system has a program-product management table stored in a shared memory in the storage subsystem and showing presence or absence of the program products, which provide management functions of respective resources to respective SLPRs. At the time of executing the management functions by the program products in the SLPRs of users in accordance with instructions from the users, the storage management system is referred to and execution of the management function having no program product is restricted.Type: GrantFiled: March 28, 2011Date of Patent: June 26, 2012Assignee: Hitachi, Ltd.Inventors: Shuichi Yagi, Kozue Fujii, Tatsuya Murakami
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Publication number: 20110173390Abstract: There is provided a storage management system capable of utilizing division management with enhanced flexibility and of enhancing security of the entire system, by providing functions by program products in each division unit of a storage subsystem. The storage management system has a program-product management table stored in a shared memory in the storage subsystem and showing presence or absence of the program products, which provide management functions of respective resources to respective SLPRs. At the time of executing the management functions by the program products in the SLPRs of users in accordance with instructions from the users, the storage management system is referred to and execution of the management function having no program product is restricted.Type: ApplicationFiled: March 28, 2011Publication date: July 14, 2011Inventors: Shuichi Yagi, Kozue Fujii, Tatsuya Murakami
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Patent number: 7917704Abstract: There is provided a storage management system capable of utilizing division management with enhanced flexibility and of enhancing security of the entire system, by providing functions by program products in each division unit of a storage subsystem. The storage management system has a program-product management table stored in a shared memory in the storage subsystem and showing presence or absence of the program products, which provide management functions of respective resources to respective SLPRs. At the time of executing the management functions by the program products in the SLPRs of users in accordance with instructions from the users, the storage management system is referred to and execution of the management function having no program product is restricted.Type: GrantFiled: July 25, 2008Date of Patent: March 29, 2011Assignee: Hitachi, Ltd.Inventors: Shuichi Yagi, Kozue Fujii, Tatsuya Murakami
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Patent number: 7877520Abstract: Configuration information settings for a storage device are made highly reliable and facilitated. The storage device includes a service processor for setting storage device configuration information, and a terminal device connected to the service processor via a private line to send a command group, received from an operator and related to the storage device configuration information, to the service processor. The service processor also includes a device for determining approval or denial of execution of the command group prior to execution of the command group received from the terminal device.Type: GrantFiled: June 8, 2009Date of Patent: January 25, 2011Assignee: Hitachi, Ltd.Inventors: Toshimichi Kishimoto, Yoshinori Igarashi, Shuichi Yagi
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Publication number: 20110012110Abstract: A gallium nitride based field effect transistor having good current hysteresis characteristics in which forward gate leakage can be reduced. In a gallium nitride-based field effect transistor (100) having a gate insulation film (108), part or all of a material constituting the gate insulation film (108) is a dielectric material having a relative dielectric constant of 9-22, and a semiconductor crystal layer A (104) in contact with the gate insulation film (108) and a semiconductor crystal layer B (103) in the vicinity of the semiconductor crystal layer A (104) and having a larger electron affinity than the semiconductor crystal layer A (104) constitute a hetero junction. A hafnium oxide such as HfO2, HfAlO, HfAlON or HfSiO is preferably contained, at least partially, in the material constituting the gate insulation film (108).Type: ApplicationFiled: March 16, 2007Publication date: January 20, 2011Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Hiroyuki Sazawa, Mitsuaki Shimizu, Shuichi Yagi, Hajime Okumura
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Publication number: 20100031062Abstract: The present invention provides a storage device and a data processing method of the storage device which can prevent leaking of data attributed to stealing or taking out of a disk device. A storage device includes: a plurality of disk adapters each of which is connected to HDDs which constitutes at least one RAID group; and a management part which manages a storage area provided by the plurality of HDD in a state that the storage area is divided into a plurality of logical storage areas, and manages the plurality of RAID groups. The management part sets an encryption state indicative of whether or not the data is to be encrypted with respect to the RAID group when all of the disk adapters connected to the HDD which belong to the RAID group are the encryption adapters the data, and the encryption adapter encrypts, based on the encryption state set with respect to the RAID group, and stores the encrypted data in the HDD.Type: ApplicationFiled: September 22, 2008Publication date: February 4, 2010Inventors: Shin Nishihara, Shuichi Yagi, Yasuyuki Nagasoe
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Publication number: 20090327758Abstract: A storage apparatus is provided, which allows a user to properly use an encrypted text and a plain text even when the storage apparatus has an encrypting function. An adaptor controlling transmission and reception of data to and from a memory device is provided with an encrypting function. Data requiring no encryption is transmitted to an adaptor having no encrypting function, and data to be encrypted is transmitted to the adaptor having an encrypting function. Thus, a user of the storage apparatus can properly use an encrypted text and a plain text.Type: ApplicationFiled: August 15, 2008Publication date: December 31, 2009Inventors: Toshimitu SAKANAKA, Shuichi YAGI, Yasuyuki NAGASOE, Kenichi NISHIKAWA
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Patent number: 7603507Abstract: The present invention uses memory resources effectively and connects each storage device by a plurality of paths in a switchable manner, thus improving reliability and ease of use, by virtualizing external memory resources as internal memory resources. External storage 2 is connected to the main storage 1, and the actual volume 2A is mapped onto the virtual volume 1A. A plurality of paths is connected between the storage 1 and 2. When a failure occurs in a path in use (S3), the path having the next highest priority is selected (S4), and processing is continued using this path (S5).Type: GrantFiled: May 16, 2008Date of Patent: October 13, 2009Assignee: Hitachi, Ltd.Inventors: Shuichi Yagi, Dai Taninaka, Takao Mashima
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Publication number: 20090248905Abstract: Configuration information settings for a storage device are made highly reliable and facilitated. The storage device includes a service processor for setting storage device configuration information, and a terminal device connected to the service processor via a private line to send a command group, received from an operator and related to the storage device configuration information, to the service processor. The service processor also includes a device for determining approval or denial of execution of the command group prior to execution of the command group received from the terminal device.Type: ApplicationFiled: June 8, 2009Publication date: October 1, 2009Applicant: Hitachi, Ltd.Inventors: Toshimichi KISHIMOTO, Yoshinori Igarashi, Shuichi Yagi