Patents by Inventor Shuichiro Yamamoto
Shuichiro Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10031243Abstract: A photon counting detector is provided for electrometric waves having a wide wavelength range, such as X-rays, gamma rays, and excited weak fluorescence, by use of a common detecting structure. The detector includes an optical connecting part opposed to an emission surface of a columnar-body array and can adjust a spreading range of light emitted from an emission end face of each of a plurality of columnar bodies. The detector also includes a group of APD (avalanche photodiode) clusters opposed to the emission surface via the optical connecting part. In the group of APD clusters, N×N (N is a positive integer of 2 or more) APDs each having a light receiving face are arranged two-dimensionally and the output signals from the N×N APDs are combined by a wired logical addition circuit so as to form an APD cluster serving as one pixel. A plurality of such clusters are arranged two-dimensionally.Type: GrantFiled: October 13, 2015Date of Patent: July 24, 2018Assignee: JOB CORPORATIONInventors: Tsutomu Yamakawa, Shuichiro Yamamoto
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Patent number: 10024807Abstract: Frame data of tomographic planes that are parallel in the scan direction and between an X-ray tube and an X-ray detecting unit is generated based on detected frame data. The generation of frame data is based on the fan-shaped spreading of an X-ray beam and the differences in position in a height direction between the tomographic planes from a detection surface. Tomographic images are respectively generated from the frame data of the tomographic planes based on laminography technique. Edge information based on the changes in pixel values in each tomographic image is calculated for each pixel. A three-dimensional distribution of the edge information is generated and the edge information is searched in a direction passing through the tomographic planes and pixels indicating a maximum value in the edge information are detected. Only pixels in the tomographic images that positionally correspond to detected pixels are combined into a single composite image.Type: GrantFiled: January 23, 2015Date of Patent: July 17, 2018Assignee: JOB CORPORATIONInventors: Tsutomu Yamakawa, Shuichiro Yamamoto, Masashi Yamazaki
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Publication number: 20180069534Abstract: An electronic circuit includes: a bistable circuit connected between first and second power sources respectively supplied with first and second power-supply voltages and including first and second inverters connected in a loop being inverter circuits switching between first and second modes; a control circuit outputting first and second signals respectively setting the inverter circuits in the first and second modes to the inverter circuits; and a power-supply circuit supplying a first voltage as a power-supply voltage while the inverter circuits are in the first mode, and supplying a second voltage higher than the first voltage as the power-supply voltage while the inverter circuits are in the second mode, wherein the first mode exhibits hysteresis in a transfer characteristic curve and the second mode exhibits no hysteresis in a transfer characteristic curve, and/or the first mode has a steeper transfer characteristic curve than the second mode.Type: ApplicationFiled: March 24, 2016Publication date: March 8, 2018Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Satoshi Sugahara, Shuichiro Yamamoto
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Patent number: 9842992Abstract: A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.Type: GrantFiled: March 6, 2015Date of Patent: December 12, 2017Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Satoshi Sugahara, Yusuke Shuto, Minoru Kurosawa, Hiroshi Funakubo, Shuichiro Yamamoto
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Publication number: 20170229179Abstract: A memory circuit includes: cells arranged in rows and columns so that the rows are grouped to form banks each including one or more rows, each cell including: a bistable circuit storing data; and a non-volatile element storing data stored in the bistable circuit in a non-volatile manner and restoring data stored in a non-volatile manner to the bistable circuit; and a controller that performs a store operation on each row in turn; sets a voltage supplied, as a power-supply voltage, to cells in a first bank, which includes a row on which the store operation is performed, of the banks to a first voltage; and sets a voltage supplied, as a power-supply voltage, to cells in a bank of the banks other than the first bank to a second voltage that is less than the first voltage but at which data in the bistable circuit is retained.Type: ApplicationFiled: August 6, 2015Publication date: August 10, 2017Applicants: JAPAN SCIENCE AND TECHNOLOGY AGENCY, KANAGAWA ACADEMY OF SCIENCE AND TECHNOLOGYInventors: Satoshi Sugahara, Yusuke Shuto, Shuichiro Yamamoto
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Publication number: 20170205516Abstract: A photon counting detector is provided for electrometric waves having a wide wavelength range, such as X-rays, gamma rays, and excited weak fluorescence, by use of a common detecting structure. The detector includes an optical connecting part opposed to an emission surface of a columnar-body array and can adjust a spreading range of light emitted from an emission end face of each of a plurality of columnar bodies. The detector also includes a group of APD (avalanche photodiode) clusters opposed to the emission surface via the optical connecting part. In the group of APD clusters, N×N (N is a positive integer of 2 or more) APDs each having a light receiving face are arranged two-dimensionally and the output signals from the N×N APDs are combined by a wired logical addition circuit so as to form an APD cluster serving as one pixel. A plurality of such clusters are arranged two-dimensionally.Type: ApplicationFiled: October 13, 2015Publication date: July 20, 2017Inventors: Tsutomu YAMAKAWA, Shuichiro YAMAMOTO
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Patent number: 9601198Abstract: A memory circuit includes: a bistable circuit (30) that stores data; nonvolatile elements (MTJ1, MTJ2) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period.Type: GrantFiled: November 17, 2014Date of Patent: March 21, 2017Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Yusuke Shuto, Shuichiro Yamamoto, Satoshi Sugahara
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Publication number: 20170005265Abstract: A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.Type: ApplicationFiled: March 6, 2015Publication date: January 5, 2017Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Satoshi Sugahara, Yusuke Shuto, Minoru Kurosawa, Hiroshi Funakubo, Shuichiro Yamamoto
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Publication number: 20160349192Abstract: Frame data of tomographic planes that are parallel in the scan direction and between an X-ray tube and an X-ray detecting unit is generated based on detected frame data. The generation of frame data is based on the fan-shaped spreading of an X-ray beam and the differences in position in a height direction between the tomographic planes from a detection surface. Tomographic images are respectively generated from the frame data of the tomographic planes based on laminography technique. Edge information based on the changes in pixel values in each tomographic image is calculated for each pixel. A three-dimensional distribution of the edge information is generated and the edge information is searched in a direction passing through the tomographic planes and pixels indicating a maximum value in the edge information are detected. Only pixels in the tomographic images that positionally correspond to detected pixels are combined into a single composite image.Type: ApplicationFiled: January 23, 2015Publication date: December 1, 2016Inventors: Tsutomu YAMAKAWA, Shuichiro YAMAMOTO, Masashi YAMAZAKI
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Patent number: 9496037Abstract: A memory circuit includes: a bistable circuit (30) that writes data; nonvolatile elements (MTJ1, MTJ2) that store the data written in the bistable circuit into the nonvolataole element in a nonvolatile manner, and restore the data stored in a nonvolatile manner into the bistable circuit; and a determining unit (50) that does not store the data written in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is the same as the data in the nonvolatile elements, but stores the data in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is not the same as the data in the nonvolatile elements.Type: GrantFiled: November 18, 2014Date of Patent: November 15, 2016Assignee: Japan Science and Technology AgencyInventors: Shuichiro Yamamoto, Yusuke Shuto, Satoshi Sugahara
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Publication number: 20160174922Abstract: A low-energy X-ray image formation apparatus includes an X-ray generator generating X-rays having an energy spectrum showing an energy range continuously ranging from 18-30 keV (or ?37 keV), the energy range being higher in energy from an effective energy of an energy range ranging 10 to 23 keV. A detector detects the X-rays transmitted through a soft tissue of a subject or a tissue of a substance. The tissue of the substance corresponds in a contrast-to-noise ratio (CNR) to the soft tissue of the object. A console acquires an image of the soft tissue of the object or of the substance, based on a detection signal from the detector. The soft tissue and the substance are defined as a soft tissue and a substance presenting a CNR of 3.8 or more when the X-rays are radiated in a condition where an X-ray tube voltage is set at 20 kV.Type: ApplicationFiled: July 29, 2014Publication date: June 23, 2016Inventors: Yoshie KODERA, Tsutomu YAMAKAWA, Shuichiro YAMAMOTO, Yoshiharu OBATA
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Publication number: 20150070974Abstract: A memory circuit includes: a bistable circuit (30) that stores data; nonvolatile elements (MTJ1, MTJ2) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period.Type: ApplicationFiled: November 17, 2014Publication date: March 12, 2015Inventors: Yusuke Shuto, Shuichiro Yamamoto, Satoshi Sugahara
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Publication number: 20150070975Abstract: A memory circuit includes: a bistable circuit (30) that writes data; nonvolatile elements (MTJ1, MTJ2) that store the data written in the bistable circuit into the nonvolataole element in a nonvolatile manner, and restore the data stored in a nonvolatile manner into the bistable circuit; and a determining unit (50) that does not store the data written in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is the same as the data in the nonvolatile elements, but stores the data in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is not the same as the data in the nonvolatile elements.Type: ApplicationFiled: November 18, 2014Publication date: March 12, 2015Inventors: Shuichiro Yamamoto, Yusuke Shuto, Satoshi Sugahara
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Patent number: 8823033Abstract: A nitride semiconductor ultraviolet light-emitting device includes at least one first conductivity-type nitride semiconductor layer, a nitride semiconductor emission layer, at least one second conductivity-type nitride semiconductor layer and a transparent conductive film of crystallized Mgx1Zn1-x1O (0<x1<1) that can transmit 75% or more of light emitted from the emission layer, sequentially stacked in this order on a support substrate.Type: GrantFiled: November 29, 2012Date of Patent: September 2, 2014Assignee: Sharp Kabushiki KaishaInventors: Shuichiro Yamamoto, Shuichi Hirukawa, Masataka Ohta
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Publication number: 20130146916Abstract: A nitride semiconductor ultraviolet light-emitting device includes at least one first conductivity-type nitride semiconductor layer, a nitride semiconductor emission layer, at least one second conductivity-type nitride semiconductor layer and a transparent conductive film of crystallized Mgx1Zn1-x1O (0<x1<1) that can transmit 75% or more of light emitted from the emission layer, sequentially stacked in this order on a support substrate.Type: ApplicationFiled: November 29, 2012Publication date: June 13, 2013Inventors: Shuichiro YAMAMOTO, Shuichi HIRUKAWA, Masataka OHTA
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Patent number: 8295079Abstract: The present invention is a memory circuit that includes a bistable circuit that stores data; and a ferromagnetic tunnel junction device that nonvolatilely stores the data stored in the bistable circuit according to a magnetization direction of a ferromagnetic electrode free layer, the data nonvolatilely stored in the ferromagnetic tunnel junction device being able to be restored in the bistable circuit. According to the present invention, writing data to and reading data from the bistable circuit can be performed at high speed. In addition, even though a power source is shut down, it is possible to restore data nonvolatilely stored in the ferromagnetic tunnel junction devices to the bistable circuit.Type: GrantFiled: July 31, 2008Date of Patent: October 23, 2012Assignee: Tokyo Institute of TechnologyInventors: Shuichiro Yamamoto, Satoshi Sugahara
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Publication number: 20110273925Abstract: The present invention is a memory circuit that includes a bistable circuit that stores data, and a ferromagnetic tunnel junction device that nonvolatilely stores the data in the bistable circuit according to a magnetization direction of a ferromagnetic electrode free layer, the data nonvolatilely stored in the ferromagnetic tunnel junction device being able to be restored in the bistable circuit. According to the present invention, writing data to and reading data from the bistable circuit can be performed at high speed. In addition, even though a power source is shut down, it is possible to restore data nonvolatilely stored in the ferromagnetic tunnel junction devices to the bistable circuit.Type: ApplicationFiled: July 31, 2008Publication date: November 10, 2011Applicant: TOKYO INSTITUTE OF TECHNOLOGYInventors: Shuichiro Yamamoto, Satoshi Sugahara
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Patent number: 7995632Abstract: In a nitride semiconductor laser chip so structured as to suppress development of a step on nitride semiconductor layers, the substrate has the (1-100) plane as the principal plane, the resonator facet is perpendicular to the principal plane, and, in the cleavage surface forming the resonator facet, at least by one side of a stripe-shaped waveguide, an etched-in portion is formed as an etched-in region open toward the surface of the nitride semiconductor layers.Type: GrantFiled: May 30, 2008Date of Patent: August 9, 2011Assignee: Sharp Kabushiki KaishaInventors: Fumio Yamashita, Shigetoshi Ito, Shuichiro Yamamoto, Toshiyuki Kawakami
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Patent number: 7724793Abstract: At each side of a ridge stripe 110, a trench is formed as a region carved relative to a wafer surface so that, at the time of cleaving, a surface irregularity that develops at a mirror facet near an active layer is prevented from reaching the ridge stripe 110.Type: GrantFiled: November 29, 2006Date of Patent: May 25, 2010Assignee: Sharp Kabushiki KaishaInventors: Toshiyuki Kawakami, Yukio Yamasaki, Shuichiro Yamamoto
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Publication number: 20080304528Abstract: In a nitride semiconductor laser device so structured as to suppress development of a step on nitride semiconductor layers, the substrate has the (11-20) plane as the principal plane, the resonator end surface is perpendicular to the principal plane, and, in the cleavage surface forming the resonator end surface, at least by one side of a stripe-shaped waveguide, an etched-in portion is formed as an etched-in region open toward the surface of the nitride semiconductor layers.Type: ApplicationFiled: June 3, 2008Publication date: December 11, 2008Inventors: Shuichiro Yamamoto, Shigetoshi Ito, Fumio Yamashita, Toshiyuki Kawakami