Abstract: A memory device that includes a resistive-change memory element, the memory device includes: a first memory element that includes a first resistive-change layer and a first electrode connected to the first resistive-change layer; and a second memory element that includes a second resistive-change layer and a second electrode connected to the second resistive-change layer, wherein at least one of the thickness and the material of the second resistive-change layer and the area of the second electrode in contact with the second resistive-change layer is different from the corresponding one of the thickness and the material of the first resistive-change layer and the area of the first electrode in contact with the first resistive-change layer.

Abstract: A memory component includes: a first electrode; a memory layer; and a second electrode which are provided in that order, wherein the memory layer includes an ion source layer containing aluminum (Al) together with at least one chalcogen element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se), and a resistance variable layer provided between the ion source layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide.

Abstract: A storage device capable of decreasing the number of voltages necessitating control and decreasing peripheral circuit size is provided. A first pulse voltage (VBLR) is supplied from a first power source through a bit line BLR to an electrode of a variable resistive element. A second pulse voltage (VWL) for selecting a cell is supplied from a second power source through a word line WL to a control terminal of a transistor. A third pulse voltage (VBLT) is supplied from a third power source though a bit line BLT to a second input/output terminal of the transistor. At the time of rewriting information, the voltage value (VBLT) of the third power source is adjusted by an adjustment circuit. Thereby, a cell voltage and a cell current are changed (decreased or increased).

Abstract: A storage device capable of reducing a number of cycles necessary for a verify at a time of multi-bit recording is provided. An initial value of a potential difference VGS between a gate and a source of a switching transistor at the time of the verify is set to a value varied based on a resistance value level of multi-bit information. In the case of recording 2 bits when “01” is the information, an initial value VGS01 is set to be smaller than VGS=1.7 V corresponding to the target resistance value level “01”, and when “00” is the information, a value is set to be lower than VGS=2.2 V corresponding to the target resistance value level “00” and higher than the above-described VGS01. This can reduce the number of cycles necessary for the verify process.

Abstract: A memory device of a resistance variation type, in which data retaining characteristic at the time of writing is improved, is provided. The memory device includes: a plurality of memory elements in which a memory layer is provided between a first electrode and a second electrode so that data is written or erased in accordance with a variation in electrical characteristics of the memory layer; and pulse applying means applying a voltage pulse or a current pulse selectively to the plurality of memory elements. The memory layer includes an ion source layer including an ionic-conduction material and at least one kind of metallic element, and the ion source layer further contains oxygen.

Abstract: A memory element, including: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer containing an oxide, and the resistance change layer being provided on the first electrode side, and an ion source layer in a stacking structure of two or more of a unit ion source layer, the unit ion source layer including a first layer and a second layer, the first layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and an easy-to-move element that is easy to move in the memory layer, and having a density distribution of the easy-to-move element from the first electrode to the second electrode, and the second layer containing a difficult-to-move element that is difficult to move in the memory layer.

Abstract: A memory element includes: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, and an ion source layer containing one or more of metallic elements, and the ion source layer being provided on the second electrode side. The ion source layer includes a first ion source layer and a second ion source layer, the first ion source layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and being provided on the resistance change layer side, and the second ion source layer containing the chalcogen element with a content different from a content in the first ion source layer and being provided on the second electrode side.

Abstract: A memory element includes: a memory layer disposed between a first electrode and a second electrode. The memory layer includes: an ion source layer containing one or more metallic elements, and one or more chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se); and a resistance change layer disposed between the ion source layer and the first electrode, the resistance change layer including a layer which includes tellurium and nitrogen (N) and is in contact with the ion source layer.

Abstract: There are provided a memory element and a memory device excellently operating at a low current, and having the satisfactory retention characteristics. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer disposed on the first electrode side, and being in a single- or multi-layer structure including a layer containing a highest percentage of tellurium (Te) as an anionic component, and an ion source layer disposed on the second electrode side, and containing a metallic element and one or more chalcogen elements including tellurium (Te), sulfur (S), and selenium (Se) with aluminum (Al) of 27.7 atomic % or more but 47.4 atomic % or less.

Abstract: A memory cell is provided, in which a resistance value is appropriately controlled, thereby a variable resistance element may be applied with a voltage necessary for changing the element into a high or low resistance state. A storage element 10, a nonlinear resistance element 20, and an MOS transistor 30 are electrically connected in series. The storage element 10 has a nonlinear current-voltage characteristic opposite to a nonlinear current-voltage characteristic of the MOS transistor 30, and changes into a high or low resistance state in accordance with a polarity of applied voltage. The nonlinear resistance element 20 has a nonlinear current-voltage characteristic similar to the nonlinear current-voltage characteristic of the storage element 10.

Abstract: There are provided a memory element and a memory device with improved writing and erasing characteristics during operations at a low voltage and a low current. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, an ion source layer provided on the second electrode side, an intermediate layer provided between the resistance change layer and the ion source layer, and a barrier layer provided at least either between the ion source layer and the intermediate layer, or between the intermediate layer and the resistance change layer, and the barrier layer containing a transition metal or a nitride thereof.

Abstract: There are provided a memory element and a memory device with improved repetition characteristics during operations at a low voltage and current. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer disposed on the first electrode side, and an ion source layer disposed on the second electrode side, and having a resistivity of 2.8 m?cm or higher but lower than 1 ?cm.

Abstract: A storage device that improves ability of adjusting a resistance value level in recording and enables stable verification control is provided. VWL supplied from a second power source to a control terminal of a transistor is increased (increase portion: ?VWL) for every rerecording by verification control by a WL adjustment circuit. In the case where a variable resistive element is able to record multiple values, ?VWL is a value variable for every resistance value level of multiple value information. That is, ?VWL is a value variable according to magnitude relation of a variation range of recording resistance of the variable resistive element due to a current. In the region where the variation range of the recording resistance is large (source-gate voltage VGS of the transistor is small), ?VWL is small, while in the region where the variation range of the recording resistance is small (VGS is large), ?VWL is large.

Abstract: A memory element with reduced degradation of memory characteristics that is caused by deterioration of a memory layer, a method of manufacturing the memory element, and a memory device are provided. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer containing fluoride, and an ion source layer disposed between the resistance change layer and the second electrode.

Abstract: There are provided a memory element and a memory device with a smaller range of element-to-element variation of electrical characteristics. The memory element includes a first electrode, a memory layer, and a second layer in this order. The memory layer includes a resistance change layer including a plurality of layers varying in diffusion coefficient of mobile atoms, and an ion source layer disposed between the resistance change layer and the second electrode.

Abstract: A memory device of a resistance variation type, in which data retaining characteristic at the time of writing is improved, is provided. The memory device includes: a plurality of memory elements in which a memory layer is provided between a first electrode and a second electrode so that data is written or erased in accordance with a variation in electrical characteristics of the memory layer; and pulse applying means applying a voltage pulse or a current pulse selectively to the plurality of memory elements. The memory layer includes an ion source layer including an ionic-conduction material and at least one kind of metallic element, and the ion source layer further contains oxygen.

Abstract: A memory element and a memory device with improved controllability over resistance change by applied voltage are provided. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, and an ion source layer provided on the second electrode side and is higher in resistance value than the resistance change layer.

Abstract: A memory element capable of increasing capacity with an improvement of distribution of resistance in the high-resistance state, a drive method therefor, and a memory device are provided. The memory element includes first and second electrodes, and a plurality of resistance change elements electrically connected in series between the first and second electrodes, whose resistance values are reversibly changeable in response to application of a voltage to the first and second electrodes, and changeable to the same resistance state relative to the voltage application.

Abstract: A memory component includes: a first electrode; a memory layer; and a second electrode which are provided in that order, wherein the memory layer includes an ion source layer containing aluminum (Al) together with at least one chalcogen element selected from the group consisting of tellurium (Te), sulfur (S), and selenium (Se), and a resistance variable layer provided between the ion source layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide.

Abstract: A memory component includes: a first electrode; a memory layer; and a second electrode in this order, wherein the memory layer includes a high resistance layer which includes tellurium (Te) as the chief component among anion components and is formed on the first electrode side; and an ion source layer which includes at least one kind of metal element and at least one kind of chalcogen element among tellurium (Te), sulfur (S) and selenium (Se) and is formed on the second electrode side.