Patents by Inventor Shuji Eguchi
Shuji Eguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020158343Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 proved on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.Type: ApplicationFiled: April 30, 2002Publication date: October 31, 2002Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
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Patent number: 6433440Abstract: In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.Type: GrantFiled: June 5, 1998Date of Patent: August 13, 2002Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.Inventors: Masahiko Ogino, Shuji Eguchi, Akira Nagai, Takumi Ueno, Masanori Segawa, Hiroyoshi Kokaku, Toshiaki Ishii, Ichiro Anjoh, Asao Nishimura, Chuichi Miyazaki, Mamoru Mita, Norio Okabe
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Patent number: 6423571Abstract: A method of forming a semiconductor device having a multi-layered wiring structure that includes a conductor layer to be electrically connected to a packaging substrate, with the multi-layered wiring structure being provided on a circuit formation surface of a semiconductor chip. Ball-like terminals are formed, disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side. The multi-layered wiring structure is formed to include a buffer layer for relieving a thermal stress provided between the semiconductor chip and the packaging substrate, due to the packaging procedure. In the semiconductor device formed, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase signal speed.Type: GrantFiled: June 20, 2001Date of Patent: July 23, 2002Assignee: Hitachi, Ltd.Inventors: Masahiko Ogino, Akira Nagai, Shuji Eguchi, Toshiaki Ishii, Masanori Segawa, Haruo Akahoshi, Akio Takahashi, Takao Miwa, Naotaka Tanaka, Ichirou Anjou
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Publication number: 20020050636Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.Type: ApplicationFiled: October 23, 2001Publication date: May 2, 2002Inventors: Yukiharu Akiyama, Tomoaki Kudaishi, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Asao Nishimura, Ichiro Anjo, Kunihiro Tsubosaki, Chuichi Miyazaki, Hiroshi Koyama, Masanori Shibamoto, Akira Nagai, Masahiko Ogino
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Publication number: 20020047215Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.Type: ApplicationFiled: October 23, 2001Publication date: April 25, 2002Inventors: Yukiharu Akiyama, Tomoaki Kudaishi, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Asao Nishimura, Ichiro Anjo, Kunihiro Tsubosaki, Chuichi Miyazaki, Hiroshi Koyama, Masanori Shibamoto, Akira Nagai, Masahiko Ogino
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Patent number: 6371664Abstract: There is provided a method for manufacturing a photoelectronic device comprising a silicon platform (support substrate) having a groove for guiding an optical fiber, a semiconductor laser chip secured on the substrate and an optical fiber fitted in the groove at one end thereof to be secured on the support substrate wherein the optical fiber fitted in the groove is secured on the support substrate with a first bonding element constituted by an adhesive injected to fill the groove under the optical fiber; one surface of the support substrate is covered with silicone gel; the support substrate is secured in a package made of plastic; and the package is filled with the silicone gel which is a protective film transparent to light transmitted by the optical fiber and resistant to humidity.Type: GrantFiled: May 25, 2001Date of Patent: April 16, 2002Assignee: Hitachi, Ltd.Inventors: Shoichi Takahashi, Hiroshi Naka, Toshimasa Miura, Shuji Eguchi
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Publication number: 20020031672Abstract: The invention provides a packaging structure applied to an automotive component having semiconductors and electronic parts mounted on a ceramic base, characterized in that the semiconductors and electronic parts are partly or entirely sealed with a thixotropic silicone gel which has a thixotropy index of about 1.5-3.6 and a penetration depth of about 6-10 mm and a rate of change in viscosity of less than 10% of the initial value.Type: ApplicationFiled: April 3, 2001Publication date: March 14, 2002Inventors: Shuji Eguchi, Masahiko Asano, Mutsumi Watanabe, Kunito Nakatsuru, Hiroatsu Tokuda
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Publication number: 20010051393Abstract: A method of forming a semiconductor device having a multi-layered wiring structure that includes a conductor layer to be electrically connected to a packaging substrate, with the multi-layered wiring structure being provided on a circuit formation surface of a semiconductor chip. Ball-like terminals are formed, disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side. The multi-layered wiring structure is formed to include a buffer layer for relieving a thermal stress provided between the semiconductor chip and the packaging substrate, due to the packaging procedure. In the semiconductor device formed, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase signal speed.Type: ApplicationFiled: June 20, 2001Publication date: December 13, 2001Inventors: Masahiko Ogino, Akira Nagai, Shuji Eguchi, Toshiaki Ishii, Masanori Segawa, Haruo Akahoshi, Akio Takahashi, Takao Miwa, Naotaka Tanaka, Ichirou Anjou
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Patent number: 6307269Abstract: A semiconductor device including a semiconductor chip having connection terminals in a peripheral part of a main surface thereof; an elastic body disposed on the main surface leaving the connection terminals exposed; an insulating tape formed on the elastic body and having openings in areas where the connection terminals are situated; plural leads formed on the top surface of the insulating tape, one end of each lead being connected to one of the connection terminals and the other end being disposed on the elastic body; plural bump electrodes formed on the other ends of the plural leads; and a resin body for sealing the connection terminals and one end of each of the leads, wherein the insulating tape protrudes beyond the chip where the plural connection terminals are arranged, and wherein the shape of the resin body is restricted by the protruding part of the insulating tape.Type: GrantFiled: July 10, 1998Date of Patent: October 23, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Akita Electronics Co., Ltd.Inventors: Yukiharu Akiyama, Tomoaki Kudaishi, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Asao Nishimura, Ichiro Anjo, Kunihiro Tsubosaki, Chuichi Miyazaki, Hiroshi Koyama, Masanori Shibamoto, Akira Nagai, Masahiko Ogino
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Patent number: 6297073Abstract: A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.Type: GrantFiled: April 11, 2000Date of Patent: October 2, 2001Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Ryuji Kohno, Naotaka Tanaka, Akihiro Yaguchi, Tetsuo Kumazawa, Ichiro Anjoh, Hideki Tanaka, Asao Nishimura, Shuji Eguchi, Akira Nagai, Mamoru Mita
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Publication number: 20010024549Abstract: There is provided a method for manufacturing a photoelectronic device comprising a silicon platform (support substrate) having a groove for guiding an optical fiber, a semiconductor laser chip secured on the substrate and an optical fiber fitted in the groove at one end thereof to be secured on the support substrate wherein the optical fiber fitted in the groove is secured on the support substrate with a first bonding element constituted by an adhesive injected to fill the groove under the optical fiber; one surface of the support substrate is covered with silicone gel; the support substrate is secured in a package made of plastic; and the package is filled with the silicone gel which is a protective film transparent to light transmitted by the optical fiber and resistant to humidity.Type: ApplicationFiled: May 25, 2001Publication date: September 27, 2001Applicant: Hitachi, Ltd.Inventors: Shoichi Takahashi, Hiroshi Naka, Toshimasa Miura, Shuji Eguchi
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Patent number: 6282350Abstract: There is provided a method for manufacturing a photoelectronic device comprising a silicon platform (support substrate) having a groove for guiding an optical fiber, a semiconductor laser chip secured on the substrate and an optical fiber fitted in the groove at one end thereof to be secured on the support substrate wherein the optical fiber fitted in the groove is secured on the support substrate with a first bonding element constituted by an adhesive injected to fill the groove under the optical fiber; one surface of the support substrate is covered with silicone gel; the support substrate is secured in a package made of plastic; and the package is filled with the silicone gel which is a protective film transparent to light transmitted by the optical fiber and resistant to humidity.Type: GrantFiled: August 24, 1999Date of Patent: August 28, 2001Assignee: Hitachi, Ltd.Inventors: Shoichi Takahashi, Hiroshi Naka, Toshimasa Miura, Shuji Eguchi
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Patent number: 6130112Abstract: A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.Type: GrantFiled: October 6, 1998Date of Patent: October 10, 2000Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Ryuji Kohno, Naotaka Tanaka, Akihiro Yaguchi, Tetsuo Kumazawa, Ichiro Anjoh, Hideki Tanaka, Asao Nishimura, Shuji Eguchi, Akira Nagai, Mamoru Mita
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Patent number: 6114753Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250.degree. C.).Type: GrantFiled: May 16, 1997Date of Patent: September 5, 2000Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
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Patent number: 6114192Abstract: A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.Type: GrantFiled: July 14, 1998Date of Patent: September 5, 2000Assignee: Hitachi, Ltd.Inventors: Shigeharu Tsunoda, Junichi Saeki, Isamu Yoshida, Kazuya Ooji, Michiharu Honda, Makoto Kitano, Nae Yoneda, Shuji Eguchi, Kunihiko Nishi, Ichiro Anjoh, Kenichi Otsuka
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Patent number: 6114005Abstract: A laminate capable of mounting semiconductor elements thereon; comprising an insulating layer which is constituted by a resin portion of sea-island structure and a woven reinforcement. The resin portion of sea-island structure is, for example, such that a resin as islands are dispersed in a resin as a matrix. Thus, the insulating layer exhibits a coefficient of thermal expansion of 3.0.about.10 (ppm/K) in a planar direction thereof and a glass transition temperature of 150.about.300 (.degree.C.). Owing to these physical properties, thermal stresses which the laminate undergoes in packaging the semiconductor elements thereon can be reduced, so that the connections of the laminate with the semiconductor elements can be made highly reliable.Type: GrantFiled: May 20, 1997Date of Patent: September 5, 2000Assignee: Hitachi, Ltd.Inventors: Akira Nagai, Masatsugu Ogata, Shuji Eguchi, Masahiko Ogino, Toshiaki Ishii, Masanori Segawa, Hiroyoshi Kokaku, Ryo Moteki, Ichiro Anjoh
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Patent number: 6097100Abstract: A resin encapsulated semiconductor element is encapsulated with resin composition containing an organic compound selected from the group consisting of organobromine compounds, organophosphorus compounds and organonitrogen compounds, an inorganic filler, and a metal borate. The obtained resin encapsulated semiconductor element has the same flame resistance as a conventional semiconductor element which is encapsulated with a resin composition containing a halogen and antimony compound, and furthermore, has remarkably improved reliabilities regarding moisture resistance and storing at a high temperature by effects of the contained metal borate for suppressing generation of or trapping released gas components, such as halogen or phosphorus, and others.Type: GrantFiled: August 20, 1997Date of Patent: August 1, 2000Assignee: Hitachi, Ltd.Inventors: Shuji Eguchi, Yasuhide Sugawara, Toshiaki Ishii, Hiroyoshi Kokaku, Akira Nagai, Ryou Moteki, Ogino Masahiko, Masanori Segawa, Rie Hattori, Nobutake Tsuyuno, Takumi Ueno, Atsushi Nakamura, Asao Nishimura
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Patent number: 6049128Abstract: A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.Type: GrantFiled: March 19, 1997Date of Patent: April 11, 2000Assignee: Hitachi, Ltd.Inventors: Makoto Kitano, Ryuji Kohno, Naotaka Tanaka, Akihiro Yaguchi, Tetsuo Kumazawa, Ichiro Anjoh, Hideki Tanaka, Asao Nishimura, Shuji Eguchi, Akira Nagai, Mamoru Mita
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Patent number: 6028364Abstract: A semiconductor device has a multi-layered wiring structure having a conductor layer to be electrically connected to a packaging substrate, the structure being provided on a circuit formation surface of a semiconductor chip; and ball-like terminals disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side, wherein the multi-layered wiring structure includes a buffer layer for relieving a thermal stress produced between the semiconductor chip and the packaging substrate, after packaging thereof, and multiple wiring layers.Type: GrantFiled: March 19, 1997Date of Patent: February 22, 2000Assignee: Hitachi, Ltd.Inventors: Masahiko Ogino, Akira Nagai, Shuji Eguchi, Toshiaki Ishii, Masanori Segawa, Haruo Akahoshi, Akio Takahashi, Takao Miwa, Naotaka Tanaka, Ichirou Anjou
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Patent number: 5914531Abstract: A semiconductor plastic package, more particularly a preferred package structure and method for making a BGA package. A resin sealed BGA package where a supporting frame which fixedly supports semiconductor parts; i.e., an IC chip, a circuit board, or a circuit film, is sealed with resin, using a mold which is composed of an upper mold half and a lower mold half with the lower mold half having a plurality of projections, one at a position corresponding to each of the external terminals. The mold has a divisional structure which has an air vent between the divisional elements thereof.Type: GrantFiled: February 25, 1997Date of Patent: June 22, 1999Assignee: Hitachi, Ltd.Inventors: Shigeharu Tsunoda, Junichi Saeki, Isamu Yoshida, Kazuya Ooji, Michiharu Honda, Makoto Kitano, Nae Yoneda, Shuji Eguchi, Kunihiko Nishi, Ichiro Anjoh, Kenichi Otsuka