Abstract: A silver halide emulsion is disclosed, containing silver halide grains having a chloride content of not less than 90 mol %, wherein the silver halide grains each are internally doped with compound (A), compound (B) and compound (C); compounds (A) and (B) each meeting specified requirements and compound (C) being an iridium compound.

Abstract: A multiplication device for performing a multiplication operation on a multiplicand X and two fixed coefficients C1 and C2 where C1>C2. The multiplication device comprises a multiplier for multiplying multiplicand X and the average CA of the two fixed coefficients C1 and C2; a shift register for obtaining a sum of the multiplicand X data after being shifted up according to a position of a “1” bit in bit data where the bit data is the remainder coefficient obtained by subtracting average CA from fixed coefficient C1; and a selector for selecting a product obtained for one of the fixed coefficients C1 and C2. When the fixed coefficient C1 is selected, the selector outputs the sum of the product returned by the multiplier and the accumulated value obtained by the shift register; when fixed coefficient C2 is selected, the selector outputs the difference of the product returned by the multiplier minus the accumulated value obtained by the shift register.

Abstract: An adaptive equalization method updates the tap coefficient through utilization of the mean value of instantaneous gradient vectors, thereby ensuring the likelihood of pseudo transmission data that is generated from received data.

Abstract: A new separator for an alkaline cell is provided, which can prevent deformation to an end of the separator and also prevent short circuits within the cell structure when an external force is added to the cell. The separator has a characteristic that a ratio of a tensile strength of a longitudinal direction of a separator base paper and a tensile strength of a widthwise direction of the base paper is within a range of 2/1 to 1/1. The invention provides a new method of producing the separator. The method permits reliability in sealing properties of a closed bottom end and high productivity. The method has the steps of: winding the base paper to form a cylindrical body; subjecting the cylindrical body to a closed bottom forming step while the cylindrical body is held by a clamping device to maintain its cylindrical shape; heat-bonding an end of the cylindrical body to close the end; and releasing the cylindrical body from the cylindrical clamping device.

Abstract: It is an object to enlarge the phase range in which a phase error can be determined. An operating block (1) calculates a power of carriers from data DI and DQ. An ideal symbol estimating block (2a) outputs a plurality of ideal symbols which correspond to the power of carriers outputted from the operating block (1). A phase error tan(.theta.) calculating block (2b) calculates prediction phase errors between the ideal symbols and the symbol given by the data DI and DQ. A phase error determining block (3) determines a phase error from among the prediction phase errors outputted from the phase error tan(.theta.) calculating block and outputs the phase error.

Abstract: A k-bit data input and a 1-bit scan input of a scan flip-flop (21.sub.i) of a multiply-accumulation operation unit (4.sub.i) respectively receive a k-bit data output and a 1-bit scan output of a scan flip-flop (21.sub.i-1) of a multiply-accumulation operation unit (4.sub.j-1) in the previous stage. A j-bit data input and a 1-bit scan input of a scan flip-flop (22.sub.i) respectively receive a j-bit data output of an adder (3.sub.i-1) of a multiply-accumulation operation unit (4.sub.i-1)) in the previous stage and a 1-bit scan output of a scan flip-flop (22.sub.j+1) in the next stage.

Abstract: A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

Abstract: A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

Abstract: A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

Abstract: A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line.

Abstract: A silver halide emulsion comprises silver halide grains having a silver chloride content of not less than 10 mol % and a silver bromide content of not less than 0.1 mol % the silver halide grains being formed in the presence of at least one of compounds represented by the following Formula I:Formula IY.sub.n1 MBr.sub.n2 X.sub.n3wherein M represents an ion selected from the group consisting of rhenium, ruthenium, osmium, platinum, palladium, and iridium ion; Y represents a cation; X represents a ligand coordinating M; n.sub.1 represents an integer of 0 to 3; and n.sub.2 and n.sub.3 each represent an integer, provided that n.sub.2 .gtoreq.n.sub.3 and n.sub.2 +n.sub.3 =4 or 6.

Abstract: A circuit for repairing a defective memory cell between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line.

Abstract: A plurality of bit line signal IO lines L1, /L1 . . . Ln and /Ln are arranged on a memory cell array. These bit line signal IO lines are arranged to cross respective bit lines BL1, /BL1, . . . BLn and /BLn, and are connected to the corresponding bit lines, respectively. Each bit line signal IO line has an end extended to an end, in a direction perpendicular to the bit line, of a memory cell array, and is coupled at the end to a bit line peripheral circuit. Although bit line peripheral circuits could be arranged only at upper and lower ends of the bit lines in the prior art, the bit line peripheral circuits can be arranged also at the ends of the bit line signal IO lines in the invention. This can increase a degree of freedom in a layout for the bit line peripheral circuits, and thus the bit line peripheral circuits can be dispersedly arranged in a larger area.

Abstract: A method for preparing a silver halide photographic emulsion containing silver halide grains , each of which has two or more phases different in the silver halide composition, comprising a step of growing silver halide grains, in which said silver halide grains are grown by supplying a solution of water-soluble silver salt and a solution of water-soluble halide, wherein fine grains of silver halide having a solubility product smaller than that of silver halide grains present in the course of growing silver halide grains are made present in the silver halide emulsion at a time during the grain-growth, iridium ions being individually added at a time when or after starting the grain-growth.

Abstract: A silver halide photographic light-sensitive material comprising a support and provided thereon, a silver halide emulsion layer comprising silver halide grains containing at least one substance selected from the group consisting gallium, germanium, indium, thallium and compounds thereof.

Abstract: A photosensitive silver halide photographic material having a support and, provided thereon, the photographic component layers including at least one silver halide emulsion layer containing silver halide grains (1) having at least two kinds of halogens, is disclosed. The silver halide grains (1) are grown to in a system in the presence of silver halide grains (2) coexisting:with silver halide grains which are growing to the silver halide grains (1),for at least some portion of period that said silver halide grains are growing in the system,and comprising solubility product less than that of said growing silver halide grains.

Abstract: A semiconductor storage device including a plurality of blocks each having an array of memory cells includes an exclusive OR circuit provided in each of the plurality of blocks for making a determination as to whether data written in memory cells in the blocks are normally read. Exclusive OR circuits of a plurality of memory cell array blocks are connected to an OR circuit. With an output signal from the OR circuit, a determination is made as to whether a plurality of memory cell array blocks are normal or not. Since test data from a plurality of memory cell array blocks are simultaneously examined by an OR circuit, a test time for the semiconductor storage device can be reduced.

Abstract: In a SRAM of a selected word line structure, each local decoder is connected to a corresponding main word line and a corresponding Z decoder signal line. Each local decoder includes a circuit including two MOS transistors connected in series to each other which circuit has one end grounded. The corresponding local word line is connected to a node between these two transistors. Out of the corresponding main word line and the corresponding Z decoder signal line, one is connected to the gates of these transistors and the other is connected to the other end of said circuit, which the other end is not grounded. The potential on the corresponding local word line attains a high level only when the potential on the signal line connected to the gate of these two transistors, is at a logical level at which the transistor can be turned on and the potential on said one signal line is at a high level.

Abstract: A plurality of bit line signal IO lines L1, /L1, . . . Ln and /Ln are arranged on a memory cell array. These bit line signal IO lines are arranged to cross respective bit lines BL1, /BL1, . . . BLn and /BLn, and are connected to the corresponding bit lines, respectively. Each bit line signal IO line has an end extended to an end, in a direction perpendicular to the bit line, of a memory cell array, and is coupled at the end to a bit line peripheral circuit. Although bit line peripheral circuits could be arranged only at upper and lower ends of the bit lines in the prior art, the bit line peripheral circuits can be arranged also at the ends of the bit line signal IO lines in the invention. This can increase a degree of freedom in a layout for the bit line peripheral circuits, and thus the bit line peripheral circuits can be dispersedly arranged in a larger area.

Abstract: A silver halide color light-sensitive material is disclosed. The light-sensitive material comprises a support and a silver halide emulsion layer provided on the support. The emulsion layer comprises silver halide grains which have been formed in the presence of a complex of rhenium, molybdenum, iridium, rhodium, ruthenium, osmium, cadmium, zinc, palladium, platinum, gold, iron, nickel, cobalt, tungsten, or chromium each having at least one cyanate ligand, isocyanate ligand or fluminate ligand. The light-sensitive material is high in speed, low in fog and excellent in reciprocity low failure characteristics.