Patents by Inventor Shuji Nakaya
Shuji Nakaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7580316Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.Type: GrantFiled: May 12, 2008Date of Patent: August 25, 2009Assignee: Panasonics CorporationInventors: Hayashi Mitsuaki, Shuji Nakaya, Wataru Abe
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Patent number: 7567480Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.Type: GrantFiled: May 12, 2008Date of Patent: July 28, 2009Assignee: Panasonic CorporationInventors: Hayashi Mitsuaki, Shuji Nakaya, Wataru Abe
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Patent number: 7489571Abstract: A semiconductor device is provided for outputting data read from a read only storage device. The semiconductor device includes a read only storage device including memory cells, an address signal line for transmitting an address signal to each read only storage device, and a switching device to which the address signal is inputted. The address signal indicates an address of memory cells storing data to be read. The switching device includes an address storage circuit, a bit storage circuit and a switching storage circuit. The address storage circuit stores address information of a defective memory cell of the read only storage devices and detects whether or not memory cells storing data selected by an address signal includes a defective memory cell. The bit storage circuit stores bit information indicating which bit of data stored in memory cells including a defective memory cell is defective, and outputs a controlling signal.Type: GrantFiled: February 13, 2007Date of Patent: February 10, 2009Assignee: Panasonic CorporationInventors: Shuji Nakaya, Mitsuaki Hayashi
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Publication number: 20090021973Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.Type: ApplicationFiled: May 12, 2008Publication date: January 22, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mitsuaki Hayashi, Shuji Nakaya, Wataru Abe
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Publication number: 20080291714Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.Type: ApplicationFiled: May 12, 2008Publication date: November 27, 2008Applicant: MATSUSHITA ELECTRONIC INDUSTRIAL CO., LTD.Inventors: Hayashi Mitsuaki, Shuji Nakaya, Wataru Abe
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Patent number: 7420868Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.Type: GrantFiled: April 18, 2006Date of Patent: September 2, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mitsuaki Hayashi, Shuji Nakaya, Wataru Abe
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Publication number: 20080175076Abstract: A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.Type: ApplicationFiled: March 24, 2008Publication date: July 24, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mitsuaki HAYASHI, Wataru Abe, Shuji Nakaya, Masakazu Kurata
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Patent number: 7382657Abstract: A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.Type: GrantFiled: June 14, 2005Date of Patent: June 3, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mitsuaki Hayashi, Wataru Abe, Shuji Nakaya, Masakazu Kurata
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Patent number: 7379362Abstract: In semiconductor memory devices having hierarchical bit line structures, a transfer transistor provided between a main bit line and a sub-bit line hinders achievement of a high speed and a low voltage. A sub-bit line SBL in a subarray 12 is connected via a first transistor PC1 to a power source voltage, and via a second transistor NC1 to a ground voltage. A main bit line MBLj is connected via a third transistor PD1 to the power source voltage. The gate electrodes of the first transistor PC1 and the second transistor NC1 are connected to the main bit line MBLj, the gate electrode of the third transistor PD1 is connected to the sub-bit line SBL. In an initial state, a voltage of the main bit line MBLj is controlled to be at an H level, and voltages of word lines WLi1 to Wlip are controlled to be at an L level. When a read operation is performed, the voltage of the main bit line MBLj transitions to the L level, and thereafter, the voltage of a selected word line transitions to the H level.Type: GrantFiled: March 20, 2006Date of Patent: May 27, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Wataru Abe, Mituaki Hayashi, Shuji Nakaya
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Patent number: 7251184Abstract: A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.Type: GrantFiled: April 10, 2006Date of Patent: July 31, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shuji Nakaya, Wataru Abe, Mitsuaki Hayashi
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Patent number: 7239563Abstract: A semiconductor device for outputting data read from a read only storage device, includes a plurality of read only storage devices, each including memory cells, a plurality of selecting signal lines for transmitting selecting signals to the read only storage devices for indicating a read only storage device storing data to be read, an address signal line for transmitting an address signal to the read only storage devices for indicating an address of memory cells storing data to be read and a switching device. The switching device has an address storage circuit for storing address information of a defective memory cell and detecting whether or not selected memory cells include a defective memory cell, a data storage circuit for storing replacement data for memory cells including a defective memory cell, and a switching circuit.Type: GrantFiled: December 5, 2003Date of Patent: July 3, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shuji Nakaya, Mitsuaki Hayashi
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Publication number: 20070133324Abstract: A semiconductor device is provided for outputting data read from a read only storage device. The semiconductor device includes a read only storage device including memory cells, an address signal line for transmitting an address signal to each read only storage device, and a switching device to which the address signal is inputted. The address signal indicates an address of memory cells storing data to be read. The switching device includes an address storage circuit, a bit storage circuit and a switching storage circuit. The address storage circuit stores address information of a defective memory cell of the read only storage devices and detects whether or not memory cells storing data selected by an address signal includes a defective memory cell. The bit storage circuit stores bit information indicating which bit of data stored in memory cells including a defective memory cell is defective, and outputs a controlling signal.Type: ApplicationFiled: February 13, 2007Publication date: June 14, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shuji Nakaya, Mitsuaki Hayashi
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Publication number: 20060239109Abstract: A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarray 12 includes a first MOS transistor PD1 for charging a main bit line MBL1 and a second MOS transistor PS1 for charging a sub-bit line SBL1—1. The source electrode of the second MOS transistor PS1 is connected to a power source voltage, and the source electrode of the first MOS transistor PD1 is connected via a fourth MOS transistor PD2 to the power source voltage. Since there is not a resistance between the main bit line MBL1 and the sub-bit line SBL1—1, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.Type: ApplicationFiled: April 10, 2006Publication date: October 26, 2006Inventors: Shuji Nakaya, Wataru Abe, Mitsuaki Hayashi
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Publication number: 20060239105Abstract: Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.Type: ApplicationFiled: April 18, 2006Publication date: October 26, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hayashi Mitsuaki, Shuji Nakaya, Wataru Abe
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Publication number: 20060221754Abstract: In semiconductor memory devices having hierarchical bit line structures, a transfer transistor provided between a main bit line and a sub-bit line hinders achievement of a high speed and a low voltage. A sub-bit line SBL in a subarray 12 is connected via a first transistor PC1 to a power source voltage, and via a second transistor NC1 to a ground voltage. A main bit line MBLj is connected via a third transistor PD1 to the power source voltage. The gate electrodes of the first transistor PC1 and the second transistor NC1 are connected to the main bit line MBLj, the gate electrode of the third transistor PD1 is connected to the sub-bit line SBL. In an initial state, a voltage of the main bit line MBLj is controlled to be at an H level, and voltages of word lines WLi1 to Wlip are controlled to be at an L level. When a read operation is performed, the voltage of the main bit line MBLj transitions to the L level, and thereafter, the voltage of a selected word line transitions to the H level.Type: ApplicationFiled: March 20, 2006Publication date: October 5, 2006Inventors: Wataru Abe, Mituaki Hayashi, Shuji Nakaya
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Patent number: 7110307Abstract: An output end and an inverted output end of a latch circuit that is connected to an output buffer circuit are switched with each other, and thereby, the relationship between the data of “0” or “1” and the drain of a memory cell is connected or not connected to a bit line is changed. In addition, an input of a sense amplifier is fixed at the grounding potential by means of a test control signal, and thereby, positive logic is confirmed in the case where the output of the output buffer circuit is “L,” and negative logic is confirmed in the case where the output of the output buffer circuit is “H.Type: GrantFiled: December 30, 2004Date of Patent: September 19, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shuji Nakaya, Mitsuaki Hayashi, Masakazu Kurata
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Patent number: 7099214Abstract: There is provided a semiconductor memory device capable of performing high-speed reading even when the current capability of memory cells and transistors for charging is decreased, and a bit line capacitance is increased. In a sense amplifier, in addition to a P-type MOS transistor for charging, a P-type MOS transistor and a N-type MOS transistor are provided as a circuit for charging a selected bit line up to a switching level of a determination inverter included in a circuit for determining data of a memory cell, and a bit line is charged at high speed, whereby a read time is shortened.Type: GrantFiled: November 16, 2005Date of Patent: August 29, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Shuji Nakaya
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Publication number: 20060158942Abstract: A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.Type: ApplicationFiled: June 14, 2005Publication date: July 20, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mitsuaki Hayashi, Wataru Abe, Shuji Nakaya, Masakazu Kurata
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Publication number: 20060067145Abstract: There is provided a semiconductor memory device capable of performing high-speed reading even when the current capability of memory cells and transistors for charging is decreased, and a bit line capacitance is increased. In a sense amplifier, in addition to a P-type MOS transistor for charging, a P-type MOS transistor and a N-type MOS transistor are provided as a circuit for charging a selected bit line up to a switching level of a determination inverter included in a circuit for determining data of a memory cell, and a bit line is charged at high speed, whereby a read time is shortened.Type: ApplicationFiled: November 16, 2005Publication date: March 30, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Shuji Nakaya
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Patent number: 6992941Abstract: There is provided a semiconductor memory device capable of performing high-speed reading even when the current capability of memory cells and transistors for charging is decreased, and a bit line capacitance is increased. In a sense amplifier, in addition to a P-type MOS transistor for charging, a P-type MOS transistor and a N-type MOS transistor are provided as a circuit for charging a selected bit line up to a switching level of a determination inverter included in a circuit for determining data of a memory cell, and a bit line is charged at high speed, whereby a read time is shortened.Type: GrantFiled: December 4, 2003Date of Patent: January 31, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Shuji Nakaya