Patents by Inventor Shuming Xu

Shuming Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210280680
    Abstract: A MOSFET device includes an epitaxial region disposed on an upper surface of a substrate, the substrate serving as a drain region in the MOSFET device, and at least two body regions formed in the epitaxial region. The body regions are disposed proximate an upper surface of the epitaxial region and spaced laterally apart. The device further includes at least two source regions disposed in respective body regions, proximate an upper surface of the body regions, and a gate structure including at least two planar gates and a trench gate. Each of the planar gates is disposed on the upper surface of the epitaxial region and overlaps at least a portion of a corresponding body region. The trench gate is formed partially through the epitaxial region and between the body regions.
    Type: Application
    Filed: December 22, 2020
    Publication date: September 9, 2021
    Inventor: Shuming Xu
  • Patent number: 11107914
    Abstract: An LDMOS device includes a doped drift region of a first conductivity type formed on an upper surface of a substrate having a second conductivity type. A body region of the second conductivity type is formed proximate an upper surface of the doped drift region. Source and drain regions of the first conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A gate is formed over the body region and between the source and drain regions. The gate is formed on a first insulating layer for electrically isolating the gate from the body region. A shielding structure is formed over at least a portion of the doped drift region on a second insulating layer. The gate and shielding structure are spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 31, 2021
    Inventor: Shuming Xu
  • Publication number: 20210234042
    Abstract: An LDMOS device includes a doped drift region of a first conductivity type formed on an upper surface of a substrate having a second conductivity type. A body region of the second conductivity type is formed proximate an upper surface of the doped drift region. Source and drain regions of the first conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A gate is formed over the body region and between the source and drain regions. The gate is formed on a first insulating layer for electrically isolating the gate from the body region. A shielding structure is formed over at least a portion of the doped drift region on a second insulating layer. The gate and shielding structure are spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance.
    Type: Application
    Filed: January 28, 2020
    Publication date: July 29, 2021
    Inventor: Shuming Xu
  • Patent number: 10910478
    Abstract: A MOSFET device includes an epitaxial region disposed on an upper surface of a substrate, and at least two body regions formed in the epitaxial region. The body regions are disposed proximate an upper surface of the epitaxial region and spaced laterally apart. The device further includes at least two source regions disposed in respective body regions, proximate an upper surface of the body regions, and a gate structure including at least two planar gates and a trench gate. Each of the planar gates is disposed on the upper surface of the epitaxial region and overlaps at least a portion of a corresponding body region. The trench gate is formed partially through the epitaxial region and between the body regions. A drain contact disposed on a back surface of the substrate provides electrical connection with the substrate.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: February 2, 2021
    Inventor: Shuming Xu
  • Patent number: 10735044
    Abstract: An integrated front-end module (FEM) includes at least one power amplifier (PA) coupled to an antenna without inclusion of a switching element in a transmit signal path in the FEM between an output of the PA and the antenna. The FEM further includes at least one low-noise amplifier (LNA) and a switching circuit coupled in a receive signal path of the FEM between the antenna and an input of the LNA. The switching circuit is configured in a first mode to disable the PA and to connect the input of the LNA to the antenna for receiving signals from the antenna. The switching circuit is configured in a second mode to disconnect the input of the LNA from the antenna and to enable the PA for transmitting signals to the antenna.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 4, 2020
    Assignee: COOLSTAR TECHNOLOGY, INC.
    Inventor: Shuming Xu
  • Publication number: 20200220007
    Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.
    Type: Application
    Filed: March 17, 2020
    Publication date: July 9, 2020
    Inventors: Haian LIN, Shuming XU, Jacek KOREC
  • Patent number: 10629723
    Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haian Lin, Shuming Xu, Jacek Korec
  • Patent number: 10566270
    Abstract: A semiconductor device having enhanced thermal transfer includes at least one die, including a device layer in which one or more functional circuit elements are formed and a substrate supporting the device layer, and a support structure. The die is disposed on the support structure using at least one connection structure coupled between the device layer and the support structure. A back surface of the substrate is textured so as to increase a surface area of the back surface to thereby enhance thermal transfer between the substrate and an external environment.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: February 18, 2020
    Assignee: COOLSTAR TECHNOLOGY, INC.
    Inventors: Shuming Xu, Yi Zheng
  • Patent number: 10236288
    Abstract: A power semiconductor device includes a substrate of a first conductivity type, a buried layer of a second conductivity type formed in at least a portion of the substrate, and at least one epitaxial layer of the first conductivity type formed on at least a portion of an upper surface of the substrate and covering the buried layer. The epitaxial layer and the buried layer form a junction capacitor. The device further includes at least one active power transistor formed in an upper surface of the epitaxial layer and above at least a portion of the buried layer.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: March 19, 2019
    Assignee: COOLSTAR TECHNOLOGY, INC.
    Inventor: Shuming Xu
  • Patent number: 10224268
    Abstract: A semiconductor device having enhanced thermal transfer includes at least one die, including a device layer in which one or more functional circuit elements are formed and a substrate supporting the device layer, and a support structure. The die is disposed on the support structure using at least one connection structure coupled between the device layer and the support structure. A back surface of the substrate is textured so as to increase a surface area of the back surface to thereby enhance thermal transfer between the substrate and an external environment.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 5, 2019
    Assignee: COOLSTAR TECHNOLOGY, INC.
    Inventors: Shuming Xu, Yi Zheng
  • Publication number: 20190006269
    Abstract: A semiconductor device having enhanced thermal transfer includes at least one die, including a device layer in which one or more functional circuit elements are formed and a substrate supporting the device layer, and a support structure. The die is disposed on the support structure using at least one connection structure coupled between the device layer and the support structure. A back surface of the substrate is textured so as to increase a surface area of the back surface to thereby enhance thermal transfer between the substrate and an external environment.
    Type: Application
    Filed: September 5, 2018
    Publication date: January 3, 2019
    Inventors: Shuming Xu, Yi Zheng
  • Patent number: 10141271
    Abstract: A method of reducing electromagnetic interference in a semiconductor device includes: forming at least one functional circuit in a substrate of the semiconductor device; forming an integrated micro-shielding structure in the semiconductor device, the micro-shielding structure extending vertically through the substrate between a front surface and a back surface of the substrate and surrounding the functional circuit, the micro-shielding structure being configured to reduce radio frequency (RF) emissions in the semiconductor device and/or RF coupling between different functional parts of the functional circuit.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 27, 2018
    Assignee: COOLSTAR TECHNOLOGY, INC.
    Inventors: Shuming Xu, Yi Zheng
  • Patent number: 10134641
    Abstract: A method of fabricating a power semiconductor device includes: forming at least one lateral diffused metal-oxide-semiconductor (LDMOS) structure having a first fully silicided gate including a first metal silicide material; and forming at least one complementary metal-oxide-semiconductor (CMOS) structure integrated with the LDMOS structure on a same substrate, the CMOS structure having a second fully silicided gate including a second metal silicide material. The first metal silicide material preferably includes tungsten silicide and the second metal silicide material includes a material other than tungsten silicide.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: November 20, 2018
    Assignee: COOLSTAR TECHNOLOGY, INC.
    Inventor: Shuming Xu
  • Publication number: 20180331715
    Abstract: An integrated front-end module (FEM) includes at least one power amplifier (PA) coupled to an antenna without inclusion of a switching element in a transmit signal path in the FEM between an output of the PA and the antenna. The FEM further includes at least one low-noise amplifier (LNA) and a switching circuit coupled in a receive signal path of the FEM between the antenna and an input of the LNA. The switching circuit is configured in a first mode to disable the PA and to connect the input of the LNA to the antenna for receiving signals from the antenna. The switching circuit is configured in a second mode to disconnect the input of the LNA from the antenna and to enable the PA for transmitting signals to the antenna.
    Type: Application
    Filed: July 20, 2018
    Publication date: November 15, 2018
    Inventor: Shuming Xu
  • Publication number: 20180316382
    Abstract: An integrated front-end module (FEM) includes at least one power amplifier (PA) coupled to an antenna without inclusion of a switching element in a transmit signal path in the FEM between an output of the PA and the antenna. The FEM further includes at least one low-noise amplifier (LNA) and a switching circuit coupled in a receive signal path of the FEM between the antenna and an input of the LNA. The switching circuit is configured in a first mode to disable the PA and to connect the input of the LNA to the antenna for receiving signals from the antenna. The switching circuit is configured in a second mode to disconnect the input of the LNA from the antenna and to enable the PA for transmitting signals to the antenna.
    Type: Application
    Filed: January 5, 2017
    Publication date: November 1, 2018
    Inventor: Shuming Xu
  • Patent number: 10116347
    Abstract: An integrated front-end module (FEM) includes at least one power amplifier (PA) coupled to an antenna without inclusion of a switching element in a transmit signal path in the FEM between an output of the PA and the antenna. The FEM further includes at least one low-noise amplifier (LNA) and a switching circuit coupled in a receive signal path of the FEM between the antenna and an input of the LNA. The switching circuit is configured in a first mode to disable the PA and to connect the input of the LNA to the antenna for receiving signals from the antenna. The switching circuit is configured in a second mode to disconnect the input of the LNA from the antenna and to enable the PA for transmitting signals to the antenna.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 30, 2018
    Assignee: Coolstar Technology, Inc.
    Inventor: Shuming Xu
  • Patent number: 9704855
    Abstract: A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: July 11, 2017
    Assignee: CoolStar Technology, Inc.
    Inventors: Shuming Xu, Wenhua Dai
  • Publication number: 20170148784
    Abstract: A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.
    Type: Application
    Filed: November 23, 2015
    Publication date: May 25, 2017
    Inventors: Shuming Xu, Wenhua Dai
  • Patent number: 9628118
    Abstract: An RF PA is designed to operate efficiently for average powers when biased at the system supply voltage, and uses an envelope tracking power supply to boost the bias voltage to maintain good efficiency at higher powers. As a result, for a majority of the time when transmitting average power signals, the RF PA bias voltage is the system-wide supply voltage (e.g. 3.4V in cell phones), which eliminates the need for stepping down voltages. The bias voltage is boosted during the less frequent times when higher power is needed. As a result, only a boost type of DC voltage converter is needed. The efficiency of the RF PA is therefore increased because voltage conversion is required less frequently and only when higher power RF signals are transmitted.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 18, 2017
    Assignee: Coolstar Technology, Inc.
    Inventors: Shuming Xu, Wenhua Dai
  • Publication number: 20160343712
    Abstract: A method of fabricating a power semiconductor device includes: forming at least one lateral diffused metal-oxide-semiconductor (LDMOS) structure having a first fully silicided gate including a first metal silicide material; and forming at least one complementary metal-oxide-semiconductor (CMOS) structure integrated with the LDMOS structure on a same substrate, the CMOS structure having a second fully silicided gate including a second metal silicide material. The first metal silicide material preferably includes tungsten silicide and the second metal silicide material includes a material other than tungsten silicide.
    Type: Application
    Filed: February 4, 2016
    Publication date: November 24, 2016
    Inventor: Shuming Xu