Abstract: A MOSFET device includes an epitaxial region disposed on an upper surface of a substrate, the substrate serving as a drain region in the MOSFET device, and at least two body regions formed in the epitaxial region. The body regions are disposed proximate an upper surface of the epitaxial region and spaced laterally apart. The device further includes at least two source regions disposed in respective body regions, proximate an upper surface of the body regions, and a gate structure including at least two planar gates and a trench gate. Each of the planar gates is disposed on the upper surface of the epitaxial region and overlaps at least a portion of a corresponding body region. The trench gate is formed partially through the epitaxial region and between the body regions.

Abstract: An LDMOS device includes a semiconductor substrate of a first conductivity type, a doped drift region of a second conductivity type formed on at least a portion of the substrate, and a body region of the first conductivity type formed in the drift region. Source and drain regions of the second conductivity type are formed proximate an upper surface of the body region and drift region, respectively, and spaced laterally from one another. A gate structure is disposed between the source and drain regions and includes a control gate formed over the body region, and a field plate formed over the drift region, the gate structure being electrically isolated from the body and drift regions by a first insulating layer. An oxide structure is formed on a portion of the field plate and a portion of the drift region, the oxide structure overlapping a corner of the field plate.

Abstract: A high-frequency LDMOS device includes a semiconductor substrate of a first conductivity type, a doped drift region of a second conductivity type formed on the substrate, and a body region of the first conductivity type formed in the doped drift region. Source and drain regions of the second conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A first insulating layer is formed on the body and doped drift regions. A gate structure including multiple gate segments is formed on the first insulating layer. Each of the gate segments is spaced laterally from one another by a second insulating layer disposed between adjacent gate segments. A spacing between adjacent gate segments is controlled as a function of a thickness of the second insulating layer, a thickness of the first and second insulating layers being independently controlled.

Abstract: A semiconductor structure includes at least a first chip, the first chip comprising a semiconductor substrate and an active layer formed on an upper surface of the substrate, one or more lateral metal-oxide semiconductor devices being formed in the active layer of the first chip. The semiconductor structure further includes at least a first integrated capacitor disposed on a back-side of the semiconductor substrate of the first chip. The first integrated capacitor includes a first conductive layer in electrical connection with the back-side of the substrate, an insulating layer formed on at least a portion of an upper surface of the first conductive layer, and a second conductive layer formed on at least a portion of an upper surface of the insulating layer.

Abstract: A capacitor is provided for integration with a MOSFET device(s) formed on the same substrate. The capacitor comprises a first plate including a doped semiconductor layer of a first conductivity type, an insulating layer formed on an upper surface of the doped semiconductor layer, and a second plate including a polysilicon layer formed on an upper surface of the insulating layer. An inversion layer is formed in the doped semiconductor layer, beneath the insulating layer and proximate the upper surface of the doped semiconductor layer, as a function of an applied voltage between the first and second plates of the capacitor. At least one doped region of a second conductivity type, opposite the first conductivity type, is formed in the doped semiconductor layer adjacent to a drain and/or source region of the first conductivity type formed in the MOSFET device. The doped region is electrically connected to the inversion layer.

Abstract: The present invention provides a virtual keyboard for inputting Chinese characters and a configuring method thereof, an input method, and a Chinese character input system. The configuring method includes the following steps: setting a geometric layout of the virtual keyboard; and setting initials and finals on available keys of the virtual keyboard respectively using a cost function-based search algorithm so as to obtain an optimal layout of initial keys and final keys, wherein the initial keys and the final keys in the optimal layout are set based on a minimum cost function value for spelling all Chinese syllables, and the minimum cost function value is a minimum sum of weighted distances of the initial keys and the final keys for all the Chinese syllables.

Abstract: A radio frequency (RF) switch device includes a semiconductor substrate, doped with an impurity of a first conductivity type at a first doping concentration level, and a mesa extending vertically from an upper surface of the substrate and formed contiguous therewith. The mesa includes a drift region doped with the impurity of the first conductivity type at a second doping concentration level, the second doping concentration level being less than the first doping concentration level. The mesa forms a primary current conduction path in the RF switch device. The RF switch device further includes an insulator layer disposed on at least a portion of the upper surface of the substrate and sidewalls of the mesa, and at least one gate disposed on at least a portion of an upper surface of the insulator layer, the gate at least partially surrounding the mesa.

Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

Abstract: A MOSFET device includes a semiconductor substrate, serving as a drain region, and an epitaxial region disposed on an upper surface of the substrate. The MOSFET device includes multiple body regions formed in the epitaxial region, and multiple source regions. The body regions are disposed near an upper surface of the epitaxial region and spaced laterally from one another, and each of the source regions is disposed in a corresponding one of the body regions near an upper surface of the body region. The MOSFET device includes a gate structure having multiple planar gates and a trench gate. Each of the planar gates is disposed on the upper surface of the epitaxial region overlapping a corresponding body region. The trench gate is formed partially through the epitaxial region and between the body regions, an upper surface of the trench gate being recessed below the upper surface of the epitaxial region.

Abstract: A MOSFET device includes an epitaxial region disposed on an upper surface of a substrate, the substrate serving as a drain region in the MOSFET device, and at least two body regions formed in the epitaxial region. The body regions are disposed proximate an upper surface of the epitaxial region and spaced laterally apart. The device further includes at least two source regions disposed in respective body regions, proximate an upper surface of the body regions, and a gate structure including at least two planar gates and a trench gate. Each of the planar gates is disposed on the upper surface of the epitaxial region and overlaps at least a portion of a corresponding body region. The trench gate is formed partially through the epitaxial region and between the body regions.

Abstract: An LDMOS device includes a doped drift region of a first conductivity type formed on an upper surface of a substrate having a second conductivity type. A body region of the second conductivity type is formed proximate an upper surface of the doped drift region. Source and drain regions of the first conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A gate is formed over the body region and between the source and drain regions. The gate is formed on a first insulating layer for electrically isolating the gate from the body region. A shielding structure is formed over at least a portion of the doped drift region on a second insulating layer. The gate and shielding structure are spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance.

Abstract: An LDMOS device includes a doped drift region of a first conductivity type formed on an upper surface of a substrate having a second conductivity type. A body region of the second conductivity type is formed proximate an upper surface of the doped drift region. Source and drain regions of the first conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A gate is formed over the body region and between the source and drain regions. The gate is formed on a first insulating layer for electrically isolating the gate from the body region. A shielding structure is formed over at least a portion of the doped drift region on a second insulating layer. The gate and shielding structure are spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance.

Abstract: A MOSFET device includes an epitaxial region disposed on an upper surface of a substrate, and at least two body regions formed in the epitaxial region. The body regions are disposed proximate an upper surface of the epitaxial region and spaced laterally apart. The device further includes at least two source regions disposed in respective body regions, proximate an upper surface of the body regions, and a gate structure including at least two planar gates and a trench gate. Each of the planar gates is disposed on the upper surface of the epitaxial region and overlaps at least a portion of a corresponding body region. The trench gate is formed partially through the epitaxial region and between the body regions. A drain contact disposed on a back surface of the substrate provides electrical connection with the substrate.

Abstract: An integrated front-end module (FEM) includes at least one power amplifier (PA) coupled to an antenna without inclusion of a switching element in a transmit signal path in the FEM between an output of the PA and the antenna. The FEM further includes at least one low-noise amplifier (LNA) and a switching circuit coupled in a receive signal path of the FEM between the antenna and an input of the LNA. The switching circuit is configured in a first mode to disable the PA and to connect the input of the LNA to the antenna for receiving signals from the antenna. The switching circuit is configured in a second mode to disconnect the input of the LNA from the antenna and to enable the PA for transmitting signals to the antenna.

Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

Abstract: A semiconductor device having enhanced thermal transfer includes at least one die, including a device layer in which one or more functional circuit elements are formed and a substrate supporting the device layer, and a support structure. The die is disposed on the support structure using at least one connection structure coupled between the device layer and the support structure. A back surface of the substrate is textured so as to increase a surface area of the back surface to thereby enhance thermal transfer between the substrate and an external environment.

Abstract: A power semiconductor device includes a substrate of a first conductivity type, a buried layer of a second conductivity type formed in at least a portion of the substrate, and at least one epitaxial layer of the first conductivity type formed on at least a portion of an upper surface of the substrate and covering the buried layer. The epitaxial layer and the buried layer form a junction capacitor. The device further includes at least one active power transistor formed in an upper surface of the epitaxial layer and above at least a portion of the buried layer.

Abstract: A semiconductor device having enhanced thermal transfer includes at least one die, including a device layer in which one or more functional circuit elements are formed and a substrate supporting the device layer, and a support structure. The die is disposed on the support structure using at least one connection structure coupled between the device layer and the support structure. A back surface of the substrate is textured so as to increase a surface area of the back surface to thereby enhance thermal transfer between the substrate and an external environment.

Abstract: A semiconductor device having enhanced thermal transfer includes at least one die, including a device layer in which one or more functional circuit elements are formed and a substrate supporting the device layer, and a support structure. The die is disposed on the support structure using at least one connection structure coupled between the device layer and the support structure. A back surface of the substrate is textured so as to increase a surface area of the back surface to thereby enhance thermal transfer between the substrate and an external environment.