Abstract: The invention relates to a method of making an integrated circuit inductor that comprises a silicon substrate and an oxide layer on the silicon substrate. In one aspect, the method comprises depositing an inductive loop on the oxide layer, and making a plurality of apertures in the oxide layer beneath the inductive loop. The method also comprises providing a plurality of bridges adjacent the apertures and provided by portions of the oxide layer between an inner region within the inductive loop and an outer region of the oxide layer without the inductive loop, the inductive loop being supported on the bridges. The method comprises forming a trench in the silicon substrate beneath the bridges, to provide an air gap between the inductive loop and the silicon substrate.

Abstract: In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor power handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.

Abstract: An inductor has a spiral aluminum track deposited on an oxide layer over a silicon substrate. The substrate is etched away to form a trench, which extends around beneath the track and provides an air gap having a low dielectric constant. The oxide layer has an inner region within the track, an outer region outside the track and a bridging region extending between the other regions. The bridging region is comprised of intact bridges and gaps therebetween, which are open to the trench and through which an etchant has access to the silicon substrate to form the trench by etching.

Abstract: In the prior art LDMOSFET devices capable of handling high power have been made by locating the source contact on the bottom surface of the device, allowing for good heat sinking, with connection to the source region being made through a sinker. However, this structure has poor high frequency characteristics. Also in the prior art, good high frequency performance has been achieved by introducing a dielectric layer immediately below the source/drain regions (SOI) but this structure has poor handling capabilities. The present invention achieves both good high frequency behavior as well as good power capability in the same device. Instead of inserting a dielectric layer over the entire cross-section of the device, the dielectric layer is limited to being below the heavily doped section of the drain with a small amount of overlap into the lightly doped section. The structure is described in detail together with a process for manufacturing it.

Abstract: With a self-protect thyristor, having a MOSFET (M1) that is connected in series with the thyristor and a second, self-controlled MOSFET (M2) between the p-base of the thyristor and the external cathode (KA), several unit cells for the thyristor are arranged parallel connected in a semiconductor wafer. The voltage at the series MOSFET (M1) functions as an indicator for the overcurrent and excess temperature, and an additional MOSFET (M4) is provided where source (region) is connected conducting to the source of the series MOSFET (M1), where drain is conductivity connected with the gate of the series MOSFET (M1) and where gate conductivity connected with the drain of the series MOSFET (M1). A resistance (Rg) is provided between the gate electrode (G1) of the series MOSFET (M1) and the gate (G) of the thyristor.

Abstract: A VD (vertical diffusion) MOSFET device for use in RF power applications has a split gate structure and an additional, dummy gate is provided between the spaced apart gates and, in operation of the device, is electrically coupled to source electrodes provided outside of the gates. The split gate structure reduces gate overlap capacitance and the dummy gate induces depletion in the semiconductor body of the device and reduces the substrate capacitance. The gate overlap capacitance and the substrate capacitance both contribute to the feedback capacitance of the device which has to be as low as possible for high frequency operation. By reducing both of these components, the invention provides advantageous high frequency operation.

Abstract: An inductor has a spiral aluminum track deposited on an oxide layer over a silicon substrate. The substrate is etched away to form a trench, which extends around beneath the track and provides an air gap having a low dielectric constant. The oxide layer has an inner region within the track, an outer region outside the track and a bridging region extending between the other regions. The bridging region is comprised of intact bridges and gaps therebetween, which are open to the trench and through which an etchant has access to the silicon substrate to form the trench by etching.

Abstract: In an emitter-switched thyristor with a main thyristor (TH) composed of a p+ anode emitter (1), a drift zone (3') of opposite conductivity type, a zone (4) which has in the switched-off state a blocking zone with respect to zone (3) and an emitter zone (5) at the cathode side, again with an opposite conductivity type, so that a p+n-pn+ zone sequence results, a transistor structure (T) composed of the first three zones of alternating conductivity is provided in parallel thereto with an emitter (1), base (3) and a collector (8). This structure contains a NMOSFET (M1) for directly driving the cathode emitters (5) through the cathode connection (KA). The source of this transistor is contacted by the cathode, as well as the collector zone (8) which forms the channel zone of the MOSFET at the surface of the semiconductor. The corresponding drain zone is connected to the n+ cathode emitter (5) of the main thyristor (TH) by an electric conductor (6).