Abstract: A reverse control method includes the following operations: connecting an electronic device through an image transmission interface in a display device to receive image data from the electronic device and display the image data; connecting a control device through the display device to receive a first command from the control device; and transmitting, by the control device, the first command to the electronic device through the image transmission interface to operate as a human interface device connected to the electronic device, such that the electronic device operates in response to the first command.

Abstract: A computer-implemented method for detecting a cardiac dysfunction in a user includes obtaining, from a sensor, photoplethysmogram (PPG) signals indicative of a cardiac rhythm of the user. The computer-implemented method further includes processing, in a computing device, the PPG signals to generate a cardiac dysfunction prediction for the user based, at least in part, on the PPG signals. The computer-implemented method further includes providing, via an annunciator, the cardiac dysfunction prediction for the user as an output.

Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

Abstract: A planning method for a displaying device, comprising: read and decode a device description file with a host of a planning system; display a planning interface on a screen via the host; take an object configuration step to configure at least one graphical object to the at least one display page and set an object parameter of the at least one graphical object; generate a corresponding graphical user interface configuration file via the host. When the planning system is connected to the displaying device, the host transmits the graphical user interface configuration file to the displaying device. A microcontroller of the displaying device displays a corresponding graphical user interface on the displaying module based on the graphical user interface configuration file. In this way, the operation time for the user to plan the graphical user interface could be effectively saved.

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

Abstract: Various embodiments are described herein for a system, method, and device for automated detection of focal source locations of electrophysiological activity in an organ. The system, method and device may also be used to guide catheter ablation of the organ. An electrogram signal can be obtained from a location in the organ, and it can be determined if the electrogram is periodic. If so, the corresponding unipolar electrogram can be input to a deep learning neural network classification model trained to generate a unipolar electrogram classification result in response to receiving the unipolar electrogram as an input. The location can be identified as a focal source location or a non-focal source location based on the unipolar electrogram classification result.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A light-guide optical element is provided, including a transparent light-guide body having a first inclined surface and a second inclined surface disposed therein. The transparent light-guide body includes a side surface facing a first direction, and a first surface and a second surface which are adjacent to the side surface and face each other. The first inclined surface extends from the first surface to the second surface. The second inclined surface is located at the other side of the first inclined surface facing the side surface. The second inclined surface extends from the first surface to the second surface. When an input light enters the transparent light-guide body, the input light is partially reflected by the first inclined surface and the second inclined surface to form an output light output from the transparent light-guide body.

Abstract: A head up display device includes a pancake lens and a picture generation unit. The pancake lens includes a half mirror and a reflective polarizer. The half mirror has a light incident surface and a reflective surface. The reflective polarizer is disposed on the reflective surface and combined with the half mirror for forming a reflective space. The picture generation unit is disposed in the direction of the pancake lens opposite to the user's eyes. The picture generation unit generates image light and the image light enters the reflective space from the light incident surface. After the reflection, the image light is directed towards the user's eyes to form a virtual image. The optical path of the virtual image and the image light has a un-axis angle.

Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

Abstract: A diode package for series circuit includes a plurality of conductive bearing frames, a plurality of diode chips and a plurality of conductive bridging frames. Each the bearing frame has a chip setting portion or a bridging portion, or has a chip setting portion and a bridging portion bent in the chip setting portion. Each the diode chip is disposed on each chip setting portion. Each the bridging frame bridges between two adjacent bearing frames. Two ends of each the bridging frame are respectively connected to each the diode chip and each the bridging portion to form a series structure.

Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.