Patents by Inventor Shun Liao

Shun Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11940737
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Publication number: 20240096083
    Abstract: A computer-implemented method for determining scene-consistent motion forecasts from sensor data can include obtaining scene data including one or more actor features. The computer-implemented method can include providing the scene data to a latent prior model, the latent prior model configured to generate scene latent data in response to receipt of scene data, the scene latent data including one or more latent variables. The computer-implemented method can include obtaining the scene latent data from the latent prior model. The computer-implemented method can include sampling latent sample data from the scene latent data. The computer-implemented method can include providing the latent sample data to a decoder model, the decoder model configured to decode the latent sample data into a motion forecast including one or more predicted trajectories of the one or more actor features.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Sergio Casas, Cole Christian Gulino, Shun Da Suo, Katie Z. Luo, Renjie Liao, Raquel Urtasun
  • Publication number: 20240096998
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG
  • Patent number: 11935981
    Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 19, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chu-Jih Su, Chia-Hsiang Chou, Wei-Chih Peng, Wen-Luh Liao, Chao-Shun Huang, Hsuan-Le Lin, Shih-Chang Lee, Mei Chun Liu, Chen Ou
  • Publication number: 20240085676
    Abstract: A light-folding element includes an object-side surface, an image-side surface, a reflection surface and a connection surface. The reflection surface is configured to reflect imaging light passing through the object-side surface to the image-side surface. The connection surface is connected to the object-side, image-side and reflection surfaces. The light-folding element has a recessed structure located at the connection surface. The recessed structure is recessed from the connection surface an includes a top end portion, a bottom end portion and a tapered portion located between the top end and bottom end portions. The top end portion is located at an edge of the connection surface. The tapered portion has two tapered edges located on the connection surface. The tapered edges are connected to the top end and bottom end portions. A width of the tapered portion decreases in a direction from the top end portion towards the bottom end portion.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Min-Chun LIAO, Lin An CHANG, Ming-Ta CHOU, Jyun-Jia CHENG, Cheng-Feng LIN, Ming-Shun CHANG
  • Patent number: 11894437
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chih-Chien Chi, Chien-Shun Liao, Keng-Chu Lin, Kai-Ting Huang, Sung-Li Wang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang, Cheng-Wei Chang
  • Patent number: 11885996
    Abstract: A light-guide optical element is provided, including a transparent light-guide body having a first inclined surface and a second inclined surface disposed therein. The transparent light-guide body includes a side surface facing a first direction, and a first surface and a second surface which are adjacent to the side surface and face each other. The first inclined surface extends from the first surface to the second surface. The second inclined surface is located at the other side of the first inclined surface facing the side surface. The second inclined surface extends from the first surface to the second surface. When an input light enters the transparent light-guide body, the input light is partially reflected by the first inclined surface and the second inclined surface to form an output light output from the transparent light-guide body.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: January 30, 2024
    Assignee: Shinyoptics Corp.
    Inventors: Jinn-Chou Yoo, Chun-Min Chen, Cheng-Shun Liao
  • Publication number: 20230400685
    Abstract: A head up display device includes a pancake lens and a picture generation unit. The pancake lens includes a half mirror and a reflective polarizer. The half mirror has a light incident surface and a reflective surface. The reflective polarizer is disposed on the reflective surface and combined with the half mirror for forming a reflective space. The picture generation unit is disposed in the direction of the pancake lens opposite to the user's eyes. The picture generation unit generates image light and the image light enters the reflective space from the light incident surface. After the reflection, the image light is directed towards the user's eyes to form a virtual image. The optical path of the virtual image and the image light has a un-axis angle.
    Type: Application
    Filed: November 29, 2022
    Publication date: December 14, 2023
    Inventors: Jinn-Chou Yoo, Chun-Min Chen, Cheng-Shun Liao
  • Publication number: 20230387277
    Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 30, 2023
    Inventors: Jenn-Gwo Hwu, Chien-Shun Liao
  • Publication number: 20230369554
    Abstract: A diode package for series circuit includes a plurality of conductive bearing frames, a plurality of diode chips and a plurality of conductive bridging frames. Each the bearing frame has a chip setting portion or a bridging portion, or has a chip setting portion and a bridging portion bent in the chip setting portion. Each the diode chip is disposed on each chip setting portion. Each the bridging frame bridges between two adjacent bearing frames. Two ends of each the bridging frame are respectively connected to each the diode chip and each the bridging portion to form a series structure.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 16, 2023
    Inventor: HUANG-SHUN LIAO
  • Patent number: 11757025
    Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 12, 2023
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Jenn-Gwo Hwu, Chien-Shun Liao
  • Patent number: 11581259
    Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Chien-Shun Liao, Sung-Li Wang, Shuen-Shin Liang, Shu-Lan Chang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang
  • Patent number: 11563083
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: January 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Shuen-Shin Liang, Sung-Li Wang, Hsu-Kai Chang, Chia-Hung Chu, Chien-Shun Liao, Yi-Ying Liu
  • Patent number: 11563009
    Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 24, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Samuel C. Pan, Chien-Shun Liao, Kuan-Hao Tseng
  • Publication number: 20230016515
    Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Chien-Shun Liao, Sung-Li Wang, Shuen-Shin Liang, Shu-Lan Chang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang
  • Publication number: 20220367660
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chih-Chien Chi, Chien-Shun Liao, Keng-Chu Lin, Kai-Ting Huang, Sung-Li Wang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang, Cheng-Wei Chang
  • Patent number: 11502189
    Abstract: Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 15, 2022
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Jenn-Gwo Hwu, Chien-Shun Liao, Wei-Chih Kao
  • Publication number: 20220052157
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.
    Type: Application
    Filed: January 29, 2021
    Publication date: February 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei CHANG, Shuen-Shin Liang, Sung-Li Wang, Hsu-Kai Chang, Chia-Hung Chu, Chien-Shun Liao, Yi-Ying Liu
  • Publication number: 20210407925
    Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.
    Type: Application
    Filed: November 17, 2020
    Publication date: December 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei CHANG, Chien-Shun LIAO, Sung-Li WANG, Shuen-Shin LIANG, Shu-Lan CHANG, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG
  • Publication number: 20210223456
    Abstract: A light-guide optical element is provided, including a transparent light-guide body having a first inclined surface and a second inclined surface disposed therein. The transparent light-guide body includes a side surface facing a first direction, and a first surface and a second surface which are adjacent to the side surface and face each other. The first inclined surface extends from the first surface to the second surface. The second inclined surface is located at the other side of the first inclined surface facing the side surface. The second inclined surface extends from the first surface to the second surface. When an input light enters the transparent light-guide body, the input light is partially reflected by the first inclined surface and the second inclined surface to form an output light output from the transparent light-guide body.
    Type: Application
    Filed: June 2, 2020
    Publication date: July 22, 2021
    Inventors: Jinn-Chou Yoo, Chun-Min Chen, Cheng-Shun Liao