Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: A context switching method for video encoders that enables higher priority video streams to interrupt lower priority video streams. A high priority frame may be received for processing while another frame is being processed. The pipeline may be signaled to perform a context stop for the current frame. The pipeline stops processing the current frame at an appropriate place, and propagates the stop through the stages of the pipeline and to a transcoder through DMA. The stopping location is recorded. The video encoder may then process the higher-priority frame. When done, a context restart is performed and the pipeline resumes processing the lower-priority frame beginning at the recorded location. The transcoder may process data for the interrupted frame while the higher-priority frame is being processed in the pipeline, and similarly the pipeline may begin processing the lower-priority frame after the context restart while the transcoder completes processing the higher-priority frame.

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: A context switching method for video encoders that enables higher priority video streams to interrupt lower priority video streams. A high priority frame may be received for processing while another frame is being processed. The pipeline may be signaled to perform a context stop for the current frame. The pipeline stops processing the current frame at an appropriate place, and propagates the stop through the stages of the pipeline and to a transcoder through DMA. The stopping location is recorded. The video encoder may then process the higher-priority frame. When done, a context restart is performed and the pipeline resumes processing the lower-priority frame beginning at the recorded location. The transcoder may process data for the interrupted frame while the higher-priority frame is being processed in the pipeline, and similarly the pipeline may begin processing the lower-priority frame after the context restart while the transcoder completes processing the higher-priority frame.

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract: Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.

Abstract: In an embodiment, a model may be created using a register-transfer level (RTL) representation (or other cycle-accurate representation) of the controller and the circuitry in the communication fabric to the controller. The request sources may be replaced by transactors, which may generate transactions to test the performance of the fabric and controller. Accordingly, only the designs of the controller and the fabric circuitry may be needed to model performance in this embodiment. In an embodiment, at least some of the transactors may be behavioral transactors that attempt to mimic the operation of corresponding request sources. Other transactors may be statistical distributions, in some embodiments. In an embodiment, the transactors may include a transaction generator (e.g. behavioral or statistical) and a protocol translator configured to convert generated transactions to the communication protocol in use at the point that the transactor is connected to the fabric.

Abstract: Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processing system may include control circuitry configured to determine whether a device is operating in a single sensor mode (one active sensor) or a dual sensor mode (two active sensors). When operating in the single sensor mode, data may be provided directly to a front-end pixel processing unit from the sensor interface of the active sensor. When operating in a dual sensor mode, the image frames from the first and second sensors are provided to the front-end pixel processing unit in an interleaved manner. For instance, in one embodiment, the image frames from the first and second sensors are written to a memory, and then read out to the front-end pixel processing unit in an interleaved manner.

Abstract: In an embodiment, a model may be created using a register-transfer level (RTL) representation (or other cycle-accurate representation) of the controller and the circuitry in the communication fabric to the controller. The request sources may be replaced by transactors, which may generate transactions to test the performance of the fabric and controller. Accordingly, only the designs of the controller and the fabric circuitry may be needed to model performance in this embodiment. In an embodiment, at least some of the transactors may be behavioral transactors that attempt to mimic the operation of corresponding request sources. Other transactors may be statistical distributions, in some embodiments. In an embodiment, the transactors may include a transaction generator (e.g. behavioral or statistical) and a protocol translator configured to convert generated transactions to the communication protocol in use at the point that the transactor is connected to the fabric.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a system-on-a-chip processor. In the method and apparatus of the present invention both intra-virtual channel dependencies and inter-virtual channel dependencies are fully programmable, thereby offering significant advantages over prior art I/O interfaces. The method and apparatus of the present invention is broadly comprised of a system for managing data transactions between a first bus and a second bus. A first transaction conversion module is operably connected to the first bus and is operable to receive transactions from the first bus and a first format and to convert those transactions into an internal format.

Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Abstract: An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding write has reached a target device of that write. The write monitor circuit is configured to update the write response indicator in response to receiving an indication of a first write response. A computer accessible medium may comprises instructions which, when executed: (i) initialize the write response indicator; and (ii) issue one or more writes to a target device, wherein the target device is configured to response to each of the writes with a write response to be indicated by the write response indicator.