Patents by Inventor Shun Wai Go

Shun Wai Go has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040130552
    Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
    Type: Application
    Filed: June 9, 2003
    Publication date: July 8, 2004
    Inventors: Jerome F. Duluk, Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, Joseph P. Bratt, George Cuan, Stephen L. Dodgen, Emerson S. Fang, Zhaoyu Gong, Thomas Y. Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N. Papakipos, Jason R. Redgrave, Sushma S. Trivedi, Nathan D. Tuck, Shun Wai Go, Lindy Fung, Tuan D. Nguyen, Joseph P. Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan-Wei Tsay
  • Patent number: 6717576
    Abstract: A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: April 6, 2004
    Assignee: Apple Computer, Inc.
    Inventors: Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, Joseph P. Bratt, George Cuan, Stephen L. Dodgen, Emerson S. Fang, Zhaoyu Gong, Thomas Y. Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N. Papakipos, Jason R. Redgrave, Sushma S. Trivedi, Nathan D. Tuck, Shun Wai Go, Lindy Fung, Tuan D. Nguyen, Joseph P. Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan-Wei Tsay
  • Patent number: 6693639
    Abstract: A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: February 17, 2004
    Assignee: Apple Computer, Inc.
    Inventors: Jerome F. Duluk, Jr., Jack Benkual, Shun Wai Go, Sushma S. Trivedi, Richard E. Hessel, Joseph P. Bratt
  • Publication number: 20030200383
    Abstract: An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding write has reached a target device of that write. The write monitor circuit is configured to update the write response indicator in response to receiving an indication of a first write response. A computer accessible medium may comprises instructions which, when executed: (i) initialize the write response indicator; and (ii) issue one or more writes to a target device, wherein the target device is configured to response to each of the writes with a write response to be indicated by the write response indicator.
    Type: Application
    Filed: April 22, 2002
    Publication date: October 23, 2003
    Inventors: Kwong-Tak A. Chui, Shun Wai Go, Mark D. Hayter, Chun H. Ning, Amy K. Silveria
  • Patent number: 6577317
    Abstract: An apparatus and methods for rendering 3D-graphics images preferably includes a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a geometry-operations pipeline, coupled to the port and to the output, the geometry-operations pipeline including a block for performing transformations. In one embodiment, the block for performing transformations includes a co-extensive logical and first physical stages, as well as a second physical stage including multiple logical stages. The second physical stage includes multiple logical stages that interleave their execution.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: June 10, 2003
    Assignee: Apple Computer, Inc.
    Inventors: Jerome F. Duluk, Jr., Jack Benkual, Vaughn T. Arnold, Tuan D. Nguyen, Richard E. Hessel, Stephen L. Dodgen, Shun Wai Go
  • Publication number: 20030067468
    Abstract: A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
    Type: Application
    Filed: November 7, 2002
    Publication date: April 10, 2003
    Inventors: Jerome F. Duluk, Jack Benkual, Shun Wai Go, Sushma S. Trivedi, Richard E. Hessel, Joseph P. Bratt
  • Patent number: 6525737
    Abstract: A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: February 25, 2003
    Assignee: Apple Computer, Inc.
    Inventors: Jerome F. Duluk, Jr., Jack Benkual, Shun Wai Go, Sushma S. Trivedi, Richard E. Hessel, Joseph P. Bratt