Abstract: A semiconductor device includes an interconnect layer on an inter-layer dielectric (ILD) structure. The ILD structure includes: first contacts, extending through the ILD structure, electrically connected to corresponding first components located in a floor structure underlying the ILD structure; at least one second component located within the ILD structure and spaced from a surface of the ILD structure (in a direction perpendicular to a plane of the ILD structure) a distance which is less than a thickness of the ILD structure; and second contacts directly contacting corresponding first regions of the at least one second component. The interconnect layer includes: first metallization segments which directly contact corresponding ones of the first contacts; and second metallization segments located over a second region of the at least one second component, a width of the second metallization segments being less than a width of the first metallization segments.

Abstract: A method of fabricating a semiconductor device. The method includes forming a dummy structure over a substrate, forming conductive features on opposite sides of the dummy gate structure, removing the dummy structure and a portion of the substrate beneath the dummy gate structure to form a trench, and filling the trench with a dielectric material.

Abstract: A method of fabricating a semiconductor structure. The method includes forming a dummy structure over a semiconductor body. The method further includes depositing an inter-layer dielectric (ILD) over the semiconductor body. The method further includes removing a dummy material of the dummy structure to form an opening in the ILD. The method further includes filling the opening with a dielectric material to form a dielectric structure. The method further includes stacking a plurality of interconnect elements over the dielectric structure.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain and a gate on a semiconductor substrate; (ii) forming a conductive contact located on and in contact with at least one of the source and the drain; and (iii) forming a capacitor having a first electrode and a second electrode on the semiconductor substrate, in which at least one of the first and second electrodes is formed using front-end-of line (FEOL) processes or middle-end-of line (MEOL) processes.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain and a gate on a semiconductor substrate; (ii) forming a conductive contact located on and in contact with at least one of the source and the drain; and (iii) forming a capacitor having a first electrode and a second electrode on the semiconductor substrate, in which at least one of the first and second electrodes is formed using front-end-of line (FEOL) processes or middle-end-of line (MEOL) processes.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor, a conductive contact and a capacitor. The transistor is formed on the semiconductor substrate, and the transistor includes a gate, a source and a drain. The conductive contact is formed on and in contact with at least one of the source and the drain. The capacitor includes a first electrode and a second electrode spaced apart from first electrode. At least one of the first and second electrodes extends on substantially the same level as the conductive contact or the gate. A method of forming the semiconductor device is provided as well.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor, a conductive contact and a capacitor. The transistor is formed on the semiconductor substrate, and the transistor includes a gate, a source and a drain. The conductive contact is formed on and in contact with at least one of the source and the drain. The capacitor includes a first electrode and a second electrode spaced apart from first electrode. At least one of the first and second electrodes extends on substantially the same level as the conductive contact or the gate. A method of forming the semiconductor device is provided as well.

Abstract: A labeling machine includes a base with an upright cylinder integrally formed at the center thereof, a stopper detachably provided at a top end of the cylinder and a moving disk movable along the cylinder. When a compact disk is provided on the top end of the cylinder and retained by the stopper inserted into the top end of the cylinder, and a label is placed on the top surface of the moving disk, then the labeling machine is turned over, whereby the label is adhered to the compact disk.

Abstract: A CD labeling device has a base, a support detachably connected with the base and a planar disc detachably and slidably connected with the support and having a cushion securely attached on a face thereof. The CD labeling device is able to provide a smooth attachment of a label to a face of the CD to be labeled via the help of the cushion and the smooth sliding movement of the planar disc about the support.

Abstract: A polysilicon sensor is described which can be incorporated onto a silicon wafer containing integrated circuits for the purpose of detecting and monitoring electromigration(EM) in metal test stripes representative of the interconnection metallurgy used by the integrated circuits. The sensor capitalizes on the property of silicon whereby a small increase in temperature causes a large increase in carrier concentration. In this regard, the local temperature rise of an adjacent metal line undergoing EM failure manifests itself as a decrease in resistance of the sensor. The sensor is particularly suited for testing multi-level metallurgies such as those having an aluminum alloy sandwiched between metallic layers such as those used for diffusion barriers and anti-reflective coatings. Its fabrication is compatible with conventional MOSFET processes which use a self-aligned polysilicon gate.

Abstract: A polysilicon sensor is described which can be incorporated onto a silicon wafer containing integrated circuits for the purpose of detecting and monitoring electromigration(EM) in metal test stripes representative of the interconnection metallurgy used by the integrated circuits. The sensor capitalizes on the property of silicon whereby a small increase in temperature causes a large increase in carrier concentration. In this regard, the local temperature rise of an adjacent metal line undergoing EM failure manifests itself as a decrease in resistance of the sensor. The sensor is particularly suited for testing multi-level metallurgies such as those having an aluminum alloy sandwiched between metallic layers such as those used for diffusion barriers and anti-reflective coatings. Its fabrication is compatible with conventional MOSFET processes which use a self-aligned polysilicon gate.

Abstract: A polysilicon sensor is described which can be incorporated onto a silicon wafer containing integrated circuits for the purpose of detecting and monitoring electromigration(EM) in metal test stripes representative of the interconnection metallurgy used by the integrated circuits. The sensor capitalizes on the property of silicon whereby a small increase in temperature causes a large increase in carrier concentration. In this regard, the local temperature rise of an adjacent metal line undergoing EM failure manifests itself as a decrease in resistance of the sensor. The sensor is particularly suited for testing multi-level metallurgies such as those having an aluminum alloy sandwiched between metallic layers such as those used for diffusion barriers and anti-reflective coatings. Its fabrication is compatible with conventional MOSFET processes which use a self-aligned polysilicon gate.