Patents by Inventor Shunichi Saeki
Shunichi Saeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6724659Abstract: In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.Type: GrantFiled: January 8, 2003Date of Patent: April 20, 2004Assignees: Renesas Technology Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Shunichi Saeki, Hideakii Kurata, Naoki Kobayashi
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Patent number: 6714452Abstract: A non-volatile semiconductor memory device is capable of having its individual banks controlled separately from the outside, and a semiconductor disk device is capable of proceeding immediately to the next writing to a bank of non-volatile semiconductor memory device which has become ready. Each bank has the independent write operation of data from its data register to memory cells, enabling the transfer of data from the outside to the data register of the bank even during the write operation of other bank from the data register to memory cells thereof.Type: GrantFiled: July 26, 2002Date of Patent: March 30, 2004Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.Inventors: Naoki Kobayashi, Shunichi Saeki, Hideaki Kurata
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Publication number: 20040052114Abstract: In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed starting from the data having the nearer threshold voltage to the erased state. When writing each of the data having the other threshold voltages, writing of the data is simultaneously performed to a memory cell to which the data having the remoter threshold voltage from the erased state (write #2 and write #3).Type: ApplicationFiled: August 21, 2003Publication date: March 18, 2004Inventors: Naoki Kobayashi, Hideaki Kurata, Katsutaka Kimura, Takashi Kobayashi, Shunichi Saeki
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Patent number: 6687156Abstract: In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.Type: GrantFiled: July 30, 2002Date of Patent: February 3, 2004Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Takashi Kobayashi, Hideaki Kurata, Naoki Kobayashi, Hitoshi Kume, Katsutaka Kimura, Shunichi Saeki
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Patent number: 6636437Abstract: In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed within groups of threshold voltages, starting from the nearer threshold voltage to the erased state within each group. When writing each of the data having the other threshold voltages, writing of the data is performed to a memory cell beginning with those groups having the remoter threshold voltages from the erased state.Type: GrantFiled: October 1, 2002Date of Patent: October 21, 2003Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Naoki Kobayashi, Hideaki Kurata, Katsutaka Kimura, Takashi Kobayashi, Shunichi Saeki
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Publication number: 20030095440Abstract: In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.Type: ApplicationFiled: January 8, 2003Publication date: May 22, 2003Inventors: Shunichi Saeki, Hideakii Kurata, Naoki Kobayashi
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Patent number: 6556474Abstract: In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed within groups of threshold voltages, starting from the nearer threshold voltage to the erased state within each group. When writing each of the data having the other threshold voltages, writing of the data is performed to a memory cell beginning with those groups having the remoter threshold voltages from the erased state.Type: GrantFiled: October 25, 2000Date of Patent: April 29, 2003Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Naoki Kobayashi, Hideaki Kurata, Katsutaka Kimura, Takashi Kobayashi, Shunichi Saeki
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Patent number: 6525968Abstract: In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.Type: GrantFiled: June 18, 2002Date of Patent: February 25, 2003Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Shunichi Saeki, Hideakii Kurata, Naoki Kobayashi
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Publication number: 20030026146Abstract: In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed within groups of threshold voltages, starting from the nearer threshold voltage to the erased state within each group. When writing each of the data having the other threshold voltages, writing of the data is performed to a memory cell beginning with those groups having the remoter threshold voltages from the erased state.Type: ApplicationFiled: October 1, 2002Publication date: February 6, 2003Inventors: Naoki Kobayashi, Hideaki Kurata, Katsutaka Kimura, Takashi Kobayashi, Shunichi Saeki
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Publication number: 20020191442Abstract: A non-volatile semiconductor memory device is capable of having its individual banks controlled separately from the outside, and a semiconductor disk device is capable of proceeding immediately to the next writing to a bank of non-volatile semiconductor memory device which has become ready. Each bank has the independent write operation of data from its data register to memory cells, enabling the transfer of data from the outside to the data register of the bank even during the write operation of other bank from the data register to memory cells thereof.Type: ApplicationFiled: July 26, 2002Publication date: December 19, 2002Inventors: Naoki Kobayashi, Shunichi Saeki, Hideaki Kurata
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Publication number: 20020191458Abstract: In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.Type: ApplicationFiled: July 30, 2002Publication date: December 19, 2002Inventors: Takashi Kobayashi, Hideaki Kurata, Naoki Kobayashi, Hitoshi Kume, Katsutaka Kimura, Shunichi Saeki
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Publication number: 20020159295Abstract: In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.Type: ApplicationFiled: June 18, 2002Publication date: October 31, 2002Inventors: Shunichi Saeki, Hideakii Kurata, Naoki Kobayashi
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Patent number: 6445615Abstract: A non-volatile semiconductor memory device is capable of having its individual banks controlled separately from the outside, and a semiconductor disk device is capable of proceeding immediately to the next writing to a bank of non-volatile semiconductor memory device which has become ready. Each bank has the independent write operation of data from its data register to memory cells, enabling the transfer of data from the outside to the data register of the bank even during the write operation of other bank from the data register to memory cells thereof.Type: GrantFiled: January 12, 2001Date of Patent: September 3, 2002Assignees: Hitachi Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Naoki Kobayashi, Shunichi Saeki, Hideaki Kurata
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Patent number: 6438028Abstract: In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.Type: GrantFiled: July 13, 2000Date of Patent: August 20, 2002Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Takashi Kobayashi, Hideaki Kurata, Naoki Kobayashi, Hitoshi Kume, Katsutaka Kimura, Shunichi Saeki
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Patent number: 6414877Abstract: In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.Type: GrantFiled: January 26, 2001Date of Patent: July 2, 2002Assignee: Hitachi, Ltd.Inventors: Shunichi Saeki, Hideakii Kurata, Naoki Kobayashi
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Publication number: 20010010646Abstract: In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.Type: ApplicationFiled: January 26, 2001Publication date: August 2, 2001Inventors: Shunichi Saeki, Hideakii Kurata, Naoki Kobayashi
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Publication number: 20010007533Abstract: A non-volatile semiconductor memory device is capable of having its individual banks controlled separately from the outside, and a semiconductor disk device is capable of proceeding immediately to the next writing to a bank of non-volatile semiconductor memory device which has become ready. Each bank has the independent write operation of data from its data register to memory cells, enabling the transfer of data from the outside to the data register of the bank even during the write operation of other bank from the data register to memory cells thereof.Type: ApplicationFiled: January 12, 2001Publication date: July 12, 2001Inventors: Naoki Kobayashi, Shunichi Saeki, Hideaki Kurata
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Patent number: 6243290Abstract: The present invention provides a nonvolatile semiconductor memory device for multilevel data storage that simultaneously carries out programming of multilevel data and subsequent verification at a high programming throughput.Type: GrantFiled: August 25, 2000Date of Patent: June 5, 2001Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Hideaki Kurata, Naoki Kobayashi, Takashi Kobayashi, Katsutaka Kimura, Hitoshi Kume, Shunichi Saeki