Patents by Inventor Shunichi Saito

Shunichi Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11209981
    Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Shunichi Saito
  • Publication number: 20210357137
    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 18, 2021
    Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
  • Patent number: 11150821
    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
  • Publication number: 20210149565
    Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks The plurality of memory banks are configured to he arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.
    Type: Application
    Filed: September 25, 2020
    Publication date: May 20, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Dean D. Gans, Shunichi Saito
  • Patent number: 11007663
    Abstract: A device capable of separating a remnant from a product part irrespective of a shape of the remnant. The device includes a first attraction part which attracts a first part and is moved downward; a second attraction part provided movable relative to the first attraction part to attract a second part; a jig which comes into contact with a back surface of the second part to prevent the second part from moving downward; and further a position maintaining part which maintains a position of the second attraction part relative to the first attraction part when the first attraction part is moved downward to separate the first part from the second part.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: May 18, 2021
    Assignee: Fanuc Corporation
    Inventor: Shunichi Saito
  • Patent number: 10976945
    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
  • Patent number: 10850342
    Abstract: A dissimilar-metal joining tool that places a ring-shaped joining auxiliary member made of iron, on a surface of a workpiece in which a second metal plate made of non-ferrous metal is laminated on a first metal plate made of iron, coaxially with a through-hole penetrates the second metal plate, and that performs arc welding toward an inner hole of the joining auxiliary member, the dissimilar-metal joining tool includes a base attached to a distal end of a robot; an arc welding torch attached to the base; a positioning mechanism provided in the base, and places the inner hole at a joining position in the arc welding torch and holds the joining auxiliary member in a radially-positioned state; and a pressing mechanism presses the joining auxiliary member in the vicinity of an outer peripheral edge.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: December 1, 2020
    Assignee: FANUC CORPORATION
    Inventors: Toshihiko Inoue, Shunichi Saito
  • Patent number: 10788985
    Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Shunichi Saito
  • Publication number: 20200009676
    Abstract: A dissimilar-metal joining tool that places a ring-shaped joining auxiliary member made of iron, on a surface of a workpiece in which a second metal plate made of non-ferrous metal is laminated on a first metal plate made of iron, coaxially with a through-hole penetrates the second metal plate, and that performs arc welding toward an inner hole of the joining auxiliary member, the dissimilar-metal joining tool includes a base attached to a distal end of a robot; an arc welding torch attached to the base; a positioning mechanism provided in the base, and places the inner hole at a joining position in the arc welding torch and holds the joining auxiliary member in a radially-positioned state; and a pressing mechanism presses the joining auxiliary member in the vicinity of an outer peripheral edge.
    Type: Application
    Filed: June 6, 2019
    Publication date: January 9, 2020
    Applicant: FANUC CORPORATION
    Inventors: Toshihiko INOUE, Shunichi SAITO
  • Publication number: 20200004420
    Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.
    Type: Application
    Filed: June 25, 2019
    Publication date: January 2, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Dean D. Gans, Shunichi Saito
  • Publication number: 20190369894
    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
  • Patent number: 10481819
    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: November 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
  • Patent number: 10416041
    Abstract: A combustion state parameter calculation method for an internal combustion engine, which is capable of continuously calculating a combustion state parameter while properly maintaining the accuracy of the calculated parameter even when part of in-cylinder pressure sensors is in failure. In the combustion state parameter calculation method, as a combustion state parameter, a first combustion state parameter dependent on the magnitude of in-cylinder pressure is calculated based on a detection value from an in-cylinder pressure sensor, on a cylinder-by-cylinder basis. When it is determined that a characteristic abnormality failure in which the magnitude of the detection value deviates from the actual in-cylinder pressure has occurred in part of the in-cylinder pressure sensors and has not occurred in the other in-cylinder pressure sensors, the first combustion state parameter of a failure-determined cylinder is calculated based on the detection value from the other in-cylinder pressure sensors.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: September 17, 2019
    Assignees: HONDA MOTOR CO., LTD., KEIHIN CORPORATION
    Inventors: Shusuke Akazaki, Taisuke Inoue, Shunichi Saito
  • Patent number: 10372330
    Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Shunichi Saito
  • Patent number: 10289095
    Abstract: A wire electric discharge machining system according to the present invention includes: a wire electric discharge machine that relatively moves a wire electrode and a workpiece to be machined according to a program, and subjects the workpiece to be machined to electric discharge machining by the wire electrode; at least one hand; a robot which mounts the hand on a head of an arm, and operates an object to be operated; and a visual sensor that detects a position of a machined workpiece in a machining tank, which has been cut from the workpiece to be machined by the electric discharge machining, wherein the robot performs an operation of removing the machined workpiece from the machining tank, based on the position of the machined workpiece, which has been detected by the visual sensor.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 14, 2019
    Assignee: FANUC CORPORATION
    Inventor: Shunichi Saito
  • Publication number: 20190129635
    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
  • Publication number: 20190129637
    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.
    Type: Application
    Filed: July 27, 2018
    Publication date: May 2, 2019
    Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
  • Patent number: 10049722
    Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 14, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Atsuo Koshizuka
  • Publication number: 20180197595
    Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.
    Type: Application
    Filed: September 28, 2017
    Publication date: July 12, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Atsuo Koshizuka
  • Patent number: 9837137
    Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi