Abstract: An in-cylinder pressure detecting apparatus for an internal combustion engine, for detecting an in-cylinder pressure which is a pressure in a combustion chamber of the engine. The in-cylinder pressure is detected by an in-cylinder pressure detecting block, and a motoring pressure corresponding to an in-cylinder pressure when no combustion is performed in the combustion chamber, is estimated. A peak value of the detected in-cylinder pressure is obtained as a detected pressure peak value in a predetermined operating condition of the engine. An estimated motoring pressure peak value which is a peak value of the estimated motoring pressure and corresponds to the detected pressure peak value, is calculated. The detected pressure peak value is compared with the estimated motoring pressure peak value, and sensitivity correction of the in-cylinder pressure detecting block is performed based on a result of the comparison.

Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.

Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.

Abstract: In one embodiment, the information processing apparatus includes an acceleration sensor configured to detect acceleration of the information processing apparatus, and a display part configured to include a screen for displaying an image. The apparatus further includes a determination part configured to determine whether a displayed position of the image is to be corrected, based on duration of a state in which the acceleration occurs in a predetermined direction. The apparatus further includes a correction part configured to correct the displayed position of the image according to the determination made by the determination part.

Abstract: A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring is arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.

Abstract: According to one embodiment, an electronic device includes a main body unit, a hard disk drive housed inside the main body unit and including a head which performs reading and writing of data to a magnetic disk, a display unit pivotable between a first position where the display unit is laid parallel to the main body unit and a second position where the display unit is raised relative to the main body unit, a sensor which senses an angle at which the display unit is positioned, and a control unit. The control unit retracts the head to a retraction position when the sensor senses a change in the angle of the display unit.

Abstract: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.

Abstract: A memory module includes a plurality of data connectors provided along a long side of a module substrate, a plurality of memory chips and a plurality of data register buffers mounted on the module substrate, a data line that connects the data connectors and the data register buffers, and data lines that connect the data register buffers and the memory chips. Each of the data register buffers and a plurality of data connectors and a plurality of memory chips corresponding to the data register buffer are arranged side by side in a direction of a short side of the module substrate. According to the present invention, because each line length of the data lines is considerably shortened, it is possible to realize a considerably high data transfer rate.

Abstract: A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.

Abstract: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.

Abstract: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.

Abstract: A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.

Abstract: A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring are arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.

Abstract: A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.

Abstract: A fluid connector is provided with a socket, a plug and a locking mechanism for locking the plug inserted in the socket. The socket has an axial passage and a first valve mechanism, for opening and closing the axial passage. The first valve mechanism includes a valve stem having one end fixed to the socket and the other end formed with a valve seat, a sleeve-like slide member movable in the axial passage with respect to the socket in a sealing state, a first packing provided on the slide member, for opening and closing the passage in cooperation with the valve seat, and urging means for urging the slide member toward the valve seat and causing it to abut against the first packing. The plug has an end portion capable of being inserted in the socket and a plug main body formed with an axial holes. A second valve mechanism for opening and closing the axial hole is provided in the plug main body.

Abstract: A freely-detachable pipe coupling comprising a socket having plural slits each formed at a plug-connected front end area of the socket, extending in the circumferential direction of the socket, and also having stopper members each capable of coming into and out of its corresponding slit in the radial direction of the socket, a plug having a stopper groove round it to elastically stop and hold the plural stopper members therein and also having a portion whose outer diameter is substantially equal to the inner diameter of that plug-connected front end of the socket where the slits are formed, said portion of the plug serving to partly project the stopper members outside from the slits of the socket before the plural stopper members are elastically stopped and held in the stopper groove, and a sleeve freely slidably fitted onto the plug and forwarded to press the stopper members to the axial center of the socket, when the plug is pushed into the socket, to thereby elastically stop and hold the stopper members in