Patents by Inventor Shunji Kubo
Shunji Kubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11171086Abstract: A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.Type: GrantFiled: December 2, 2019Date of Patent: November 9, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shunji Kubo, Koichi Ando, Eiji Io, Hideyuki Tajima, Tetsuya Iida
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Publication number: 20210233841Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, an insulating film, a conductive film, a first electrode pad, a second electrode pad, and a third electrode pad. The semiconductor layer includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type opposite to the first conductivity type. The insulating film is formed on the semiconductor layer. The conductive film is formed on the second semiconductor region through the insulating film interposed therebetween. The first electrode pad is configured to be electrically connected with the first semiconductor region and is configured to be electrically connected with the power supply circuit. The second electrode pad is configured to be electrically connected with the second semiconductor region and is configured to allow a signal to be provided toward an external circuit through the second electrode pad.Type: ApplicationFiled: January 27, 2020Publication date: July 29, 2021Inventors: Shunji KUBO, Kazuki NIINO, Hajime HAYASHIMOTO
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Publication number: 20210167012Abstract: A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.Type: ApplicationFiled: December 2, 2019Publication date: June 3, 2021Inventors: Shunji KUBO, Koichi ANDO, Eiji IO, Hideyuki TAJIMA, Tetsuya IIDA
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Patent number: 9608108Abstract: A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an n+ drain region toward an n+ source region. The plurality of trenches each have a conducting layer therein extending in the main surface in the direction from the n+ drain region toward the n+ source region.Type: GrantFiled: August 25, 2015Date of Patent: March 28, 2017Assignee: Renesas Electronics CorporationInventors: Mikio Tsujiuchi, Kouji Tanaka, Yasuki Yoshihisa, Shunji Kubo
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Publication number: 20160064559Abstract: A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an n+ drain region toward an n+ source region. The plurality of trenches each have a conducting layer therein extending in the main surface in the direction from the n+ drain region toward the n+ source region.Type: ApplicationFiled: August 25, 2015Publication date: March 3, 2016Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Mikio TSUJIUCHI, Kouji TANAKA, Yasuki YOSHIHISA, Shunji KUBO
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Patent number: 9257551Abstract: An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).Type: GrantFiled: January 9, 2015Date of Patent: February 9, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Shunji Kubo
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Publication number: 20150115360Abstract: An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).Type: ApplicationFiled: January 9, 2015Publication date: April 30, 2015Inventor: Shunji KUBO
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Patent number: 8963199Abstract: An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).Type: GrantFiled: February 21, 2012Date of Patent: February 24, 2015Assignee: Renesas Electronics CorporationInventor: Shunji Kubo
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Publication number: 20140252441Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.Type: ApplicationFiled: May 27, 2014Publication date: September 11, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Atsushi HACHISUKA, Atsushi AMO, Tatsuo KASAOKA, Shunji KUBO
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Publication number: 20140015006Abstract: An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).Type: ApplicationFiled: February 21, 2012Publication date: January 16, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Shunji Kubo
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Publication number: 20120056302Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.Type: ApplicationFiled: November 14, 2011Publication date: March 8, 2012Applicant: Renesas Electronics CorporationInventors: Atsushi HACHISUKA, Atsushi AMO, Tatsuo KASAOKA, Shunji KUBO
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Patent number: 8072074Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).Type: GrantFiled: December 21, 2010Date of Patent: December 6, 2011Assignee: Renesas Electronics CorporationInventors: Atsushi Hachisuka, Atsushi Amo, Tatsuo Kasaoka, Shunji Kubo
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Publication number: 20110095349Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).Type: ApplicationFiled: December 21, 2010Publication date: April 28, 2011Applicant: Renesas Electronics CorporationInventors: Atsushi HACHISUKA, Atsushi AMO, Tatsuo KASAOKA, Shunji KUBO
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Patent number: 7884480Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).Type: GrantFiled: August 5, 2008Date of Patent: February 8, 2011Assignee: Renesas Electronics CorporationInventors: Atsushi Hachisuka, Atsushi Amo, Tatsuo Kasaoka, Shunji Kubo
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Patent number: 7563668Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).Type: GrantFiled: November 3, 2006Date of Patent: July 21, 2009Assignee: Renesas Technology Corp.Inventors: Atsushi Hachisuka, Atsushi Amo, Tatsuo Kasaoka, Shunji Kubo
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Publication number: 20090127607Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.Type: ApplicationFiled: January 15, 2009Publication date: May 21, 2009Applicant: RENESAS TECHNOLOGY CORPInventors: Atsushi AMO, Shunji Kubo
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Patent number: 7508022Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.Type: GrantFiled: June 22, 2007Date of Patent: March 24, 2009Assignee: Renesas Technology Corp.Inventors: Atsushi Amo, Shunji Kubo
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Patent number: 7498627Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.Type: GrantFiled: July 31, 2007Date of Patent: March 3, 2009Assignee: Renesas Technology Corp.Inventors: Atsushi Amo, Shunji Kubo
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Publication number: 20090008693Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).Type: ApplicationFiled: August 5, 2008Publication date: January 8, 2009Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Atsushi HACHISUKA, Atsushi AMO, Tatsuo KASAOKA, Shunji KUBO
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Publication number: 20080179651Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.Type: ApplicationFiled: July 31, 2007Publication date: July 31, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Atsushi Amo, Shunji Kubo