Patents by Inventor Shunji Kubo
Shunji Kubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070246762Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.Type: ApplicationFiled: June 22, 2007Publication date: October 25, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Atsushi Amo, Shunji Kubo
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Patent number: 7235836Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.Type: GrantFiled: November 16, 2005Date of Patent: June 26, 2007Assignee: Renesas Technology Corp.Inventors: Atsushi Amo, Shunji Kubo
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Publication number: 20070059885Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).Type: ApplicationFiled: November 3, 2006Publication date: March 15, 2007Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Atsushi Hachisuka, Atsushi Amo, Tatsuo Kasaoka, Shunji Kubo
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Patent number: 7145240Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).Type: GrantFiled: February 24, 2003Date of Patent: December 5, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Atsushi Hachisuka, Atsushi Amo, Tatsuo Kasaoka, Shunji Kubo
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Publication number: 20060060903Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.Type: ApplicationFiled: November 16, 2005Publication date: March 23, 2006Applicant: Renesas Technology Corp.Inventors: Atsushi Amo, Shunji Kubo
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Patent number: 7005694Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.Type: GrantFiled: July 14, 2004Date of Patent: February 28, 2006Assignee: Renesas Technology Corp.Inventors: Atsushi Amo, Shunji Kubo
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Publication number: 20050017284Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.Type: ApplicationFiled: July 14, 2004Publication date: January 27, 2005Inventors: Atsushi Amo, Shunji Kubo
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Patent number: 6774423Abstract: A memory cell part of a semiconductor substrate is formed with a cylindrical capacitor opening extending perpendicularly to the main surface of the semiconductor substrate. The cylindrical capacitor opening passes through a silicon oxide film, a silicon nitride film and another silicon oxide film in this order. A capacitor lower electrode, a dielectric film and a capacitor upper electrode are formed in the cylindrical capacitor opening along the surface of the cylindrical capacitor opening. The bottom surface of the cylindrical capacitor opening is formed below the main surface of silicon nitride film. Thus obtained is a semiconductor device capable of improving refreshability and soft error resistance.Type: GrantFiled: April 30, 2003Date of Patent: August 10, 2004Assignee: Renesas Technology Corp.Inventor: Shunji Kubo
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Publication number: 20040124457Abstract: A memory cell part of a semiconductor substrate is formed with a cylindrical capacitor opening extending perpendicularly to the main surface of the semiconductor substrate. The cylindrical capacitor opening passes through a silicon oxide film, a silicon nitride film and another silicon oxide film in this order. A capacitor lower electrode, a dielectric film and a capacitor upper electrode are formed in the cylindrical capacitor opening along the surface of the cylindrical capacitor opening. The bottom surface of the cylindrical capacitor opening is formed below the main surface of silicon nitride film. Thus obtained is a semiconductor device capable of improving refreshability and soft error resistance.Type: ApplicationFiled: April 30, 2003Publication date: July 1, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventor: Shunji Kubo
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Publication number: 20040065958Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).Type: ApplicationFiled: February 24, 2003Publication date: April 8, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Atsushi Hachisuka, Atsushi Amo, Tatsuo Kasaoka, Shunji Kubo
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Publication number: 20040067616Abstract: A technique for making it possible to miniaturize a semiconductor device having a memory device and a logic device on one semiconductor substrate even when a self-aligned process can not be utilized, i.e., a contact hole can not be self-aligned to a gate electrode. Contact holes (15, 65) are formed in an insulating layer (19) such that the contact holes (15) are located beside gate electrodes 6 while the contact holes (65) are located beside gate electrodes (56). An insulating film 35 is formed on each side face of the contact holes (15, 65). Then, contact plugs (16) filling the contact holes (15) and contact plugs (66) filling the contact holes (65) are formed.Type: ApplicationFiled: February 21, 2003Publication date: April 8, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Atsushi Hachisuka, Atsushi Amo, Tatsuo Kasaoka, Shunji Kubo
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Publication number: 20030213992Abstract: A semiconductor device is provided, in which drivability of a transistor in a peripheral circuit region is improved. The peripheral circuit region includes a second semiconductor region formed on the semiconductor substrate, a second gate insulating film thinner than a first gate insulating film, a second gate electrode formed on the second gate insulating film, and source and drain regions formed at both sides of the second gate electrodes in the second semiconductor region and doped with an impurity of first conductivity. The source and drain regions include a p-type low-concentration impurity region having an impurity of first conductivity in relatively low concentration and a p-type high-concentration impurity region having an impurity of first conductivity in relatively high concentration.Type: ApplicationFiled: November 6, 2002Publication date: November 20, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Shunji Kubo
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Publication number: 20030215997Abstract: It is an object to provide a semiconductor technique for shortening a time required for manufacturing a semiconductor device of a memory and logic mixing type. Contact plugs (17) and (67) are formed in an interlayer insulating film (14) and stopper films (13) and (15) with an upper surface thereof exposed from the stopper film (15). Then, an interlayer insulating film (18) is formed on the stopper film (15) and the contact plugs (17) and (67), and an opening portion (69) for exposing the contact plug (67) is formed in the interlayer insulating film (18). By etching only the interlayer insulating film (18) without etching the stopper film (15), the opening portion (69) can be formed. Consequently, it is possible to shorten a time required for forming the opening portion (69).Type: ApplicationFiled: October 2, 2002Publication date: November 20, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Atsushi Hachisuka, Atsushi Amo, Tatsuo Kasaoka, Shunji Kubo
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Patent number: 6642093Abstract: According to the present invention, a method for manufacturing a semiconductor device forms a cobalt silicide film 11 on source/drain regions 7a and 7b and a gate electrode 4 of transistors in the logic circuit region, making it possible to form a high-performance and highly integrated logic circuit.Type: GrantFiled: September 24, 2002Date of Patent: November 4, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shunji Kubo, Atsushi Amoo
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Publication number: 20030186491Abstract: According to the present invention, a method for manufacturing a semiconductor device forms a cobalt silicide film 11 on source/drain regions 7a and 7b and a gate electrode 4 of transistors in the logic circuit region, making it possible to form a high-performance and highly integrated logic circuit.Type: ApplicationFiled: September 24, 2002Publication date: October 2, 2003Inventors: Shunji Kubo, Atsushi Amoo
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Publication number: 20030098495Abstract: The present invention provides a semiconductor device comprising: antifuses having insulation films; and a breakdown-circuit transistor provided in a breakdown circuit for breaking down the insulation films to set the antifuses in a conductive state. The insulation films of the antifuses are made up of the same material as that for a gate insulation film of the breakdown-circuit transistor and formed such that the film thickness of the insulation films are thinner than that of the gate insulation film.Type: ApplicationFiled: May 28, 2002Publication date: May 29, 2003Inventors: Atsushi Amo, Shunji Kubo
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Patent number: 5893759Abstract: A depression having a depth not exceeding 0.1 .mu.m is formed on the surface of an epitaxial layer. An internal base region is formed just below the depression. An external base region is formed outside the depression. The depression having the above depth can suppress electric field at the end of the internal base in the neighborhood of the junction between the internal base region and the external base region.Type: GrantFiled: March 27, 1996Date of Patent: April 13, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tatsuhiko Ikeda, Shunji Kubo, Masao Yamawaki, Yasuki Yoshihisa