Patents by Inventor Shunji Tanaka

Shunji Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7119764
    Abstract: To provide a combination indicator assembly (1) of a minimized size to provide a sporty feeling and easy to view various displayed parameters while having an increased display functionality, the combination indicator assembly (1) includes a generally arcuate analog display unit (2) for displaying the number of revolutions of a vehicle engine, and a generally rectangular digital display unit (7) disposed inside the analog display unit (2). The digital display unit (7) includes a speedometer region (8), a distance meter region (9) for displaying the distance of travel of the vehicle or a coolant temperature display region (10) for displaying the temperature of a coolant used to cool an engine of the vehicle.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: October 10, 2006
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Shunji Tanaka, Keishi Fukumoto
  • Publication number: 20050242605
    Abstract: A container holder is disclosed. The container holder typically includes a concave portion which is formed on an outside of a utility vehicle and which is configured to be positioned forward of a driver's seat. A container may be put into or taken out of the container holder. The container holder has a pad configured to inhibit a container accommodated therein from disengaging from the container holder. When a small item is accommodated in the container holder, the pad serves as a lid.
    Type: Application
    Filed: April 27, 2005
    Publication date: November 3, 2005
    Inventors: Shunji Tanaka, Seiichi Ino, Naoki Hashimoto
  • Patent number: 6889243
    Abstract: A job scheduling analysis method and system are disclosed in which a job schedule is analyzed by use of historical job execution data in a computer system in which a plurality of jobs are executed in parallel. Historical execution data of a plurality of jobs and the file names of files accessed by the jobs are collected. The maximum multiplicity of jobs capable of operating in parallel on the computer system is inputted. When the file name of a file accessed by one job and the file name of a file accessed by another other job coincide with each other, an execution start condition of the plurality of jobs are determined to execute the one job and the other job at the earliest instants within the maximum job multiplicity so that the sequence of execution of processings by the one job and the other job is maintained and the execution time of the one job and the execution time of said other job do not overlap each other.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: May 3, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yuri Hondou, Hirofumi Nagasuka, Tadashi Yamagishi, Shunji Tanaka, Toshiyuki Kinoshita
  • Publication number: 20040046713
    Abstract: To provide a combination indicator assembly (1) of a minimized size to provide a sporty feeling and easy to view various displayed parameters while having an increased display functionality, the combination indicator assembly (1) includes a generally arcuate analog display unit (2) for displaying the number of revolutions of a vehicle engine, and a generally rectangular digital display unit (7) disposed inside the analog display unit (2). The digital display unit (7) includes a speedometer region (8), a distance meter region (9) for displaying the distance of travel of the vehicle or a coolant temperature display region (10) for displaying the temperature of a coolant used to cool an engine of the vehicle.
    Type: Application
    Filed: August 5, 2003
    Publication date: March 11, 2004
    Inventors: Shunji Tanaka, Keishi Fukumoto
  • Patent number: 5881283
    Abstract: A job scheduling analysis method and system are disclosed in which a job schedule is analyzed by use of historical job execution data in a computer system in which a plurality of jobs are executed in parallel. Historical execution data of a plurality of jobs and the file names of files accessed by the jobs are collected. The maximum multiplicity of jobs capable of operating in parallel on the computer system is inputted. When the file name of a file accessed by one job and the file name of a file accessed by another other job coincide with each other, an execution start condition of the plurality of jobs are determined to execute the one job and the other job at the earliest instants within the maximum job multiplicity so that the sequence of execution of processings by the one job and the other job is maintained and the execution time of the one job and the execution time of said other job do not overlap each other.
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: March 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Yuri Hondou, Hirofumi Nagasuka, Tadashi Yamagishi, Shunji Tanaka, Toshiyuki Kinoshita
  • Patent number: 5805790
    Abstract: In a fault recovery method for a multi-processor system including a main storage and a plurality of virtual machines which are assigned to a plurality of processors under control of a host operating system and a plurality of guest operating systems and which operate on the processors associated therewith, a fault occurring in one of the processors is detected to recover functions of the system.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: September 8, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Nota, Masaichiro Yoshioka, Seiji Nagai, Shunji Tanaka, Toshiyuki Kinoshita
  • Patent number: 5579605
    Abstract: An entrance door for office or residence that has a main door equipped with a sub door where the main door is set locked when the sub door is opened. Dimension of the sub door is selected as big enough for article transfer through it and small enough for avoiding human being invasion.
    Type: Grant
    Filed: October 5, 1994
    Date of Patent: December 3, 1996
    Inventor: Shunji Tanaka
  • Patent number: 5553291
    Abstract: A virtual machine control method for a supercomputer enables a plurality of virtual machines to use a vector processor. Control of the use of the vector processor is through the scalar processor. When a virtual machine requires use of the vector processor, it is first determined whether one of the other virtual machines operating systems is using the vector processor. If not, the scalar processor is dispatched to the operating system requesting use of the vector processor. If another virtual machine operating system is using the vector processor, then the operating system requesting use of the vector processor is placed in a wait state until the vector processor becomes free, whereupon the scalar processor is dispatched to the operating system that had been in the wait state. The condition of the vector processor being free can be communicated directly to the scalar processor without the intervention of the virtual machine monitor.
    Type: Grant
    Filed: September 14, 1993
    Date of Patent: September 3, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Shunji Tanaka, Hidenori Umeno, Nobuyoshi Sugama, Masaru Sato
  • Patent number: 5499379
    Abstract: A plural-OS run system in which a plurality of operating systems (OSs) capable of operating on machines of different architectures, respectively, are allowed to run on one bare machine under the control of one control program (CP) or one control means. The input/output instruction and input/output interrupt of the operating system capable of running on a machine of the same architecture as that of the bare machine are directly executed on the bare machine without need for translation of the format. The input/output instruction and the input/output interrupt of the operating system adapted to run on a machine of the architecture differing from that of the bare machine are allowed to be directly executed while translating the format.
    Type: Grant
    Filed: January 25, 1993
    Date of Patent: March 12, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Shunji Tanaka, Toru Ohtsuki, Hiroaki Sato, Hideo Sawamoto, Ryo Yamagata, Masaya Watanabe, Hidenori Umeno, Masatoshi Haraguchi
  • Patent number: 5437033
    Abstract: A system and method for continuous operation of a virtual machine system having operation modes including a guest mode in which virtual machines are operated and a nonguest mode in which a virtual machine monitor for controlling the virtual machines is operated. The continuous guest is a virtual machine which does not stop executing operation at the occurrence of a failure due to program error of the virtual machine monitor. A main storage is provided with two areas. One of the two areas is a continuous guest area having the same host absolute address in the nonguest mode as a guest absolute address in the guest mode, the area is used by the continuous guest which is a virtual machine which continues to operate on transition of the operation mode from the guest mode to the nonguest mode. The other is an area in which a program module for dispatching the continuous guest in response to the transition of the operation mode from the guest mode to the nonguest mode.
    Type: Grant
    Filed: November 4, 1991
    Date of Patent: July 25, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Taro Inoue, Hidenori Umeno, Shunji Tanaka, Tadashi Yamamoto, Toru Ohtsuki
  • Patent number: 5392409
    Abstract: In a computer system having a central processing unit, a main storage and at least one I/O device, a plurality of operating systems (OS) can simultaneously run under the control of a control program. For executing an I/O instruction using a central processing unit, a plurality of resident areas of said main storage which do not overlap one another are assigned, under the control of the control program, to the plurality of OSs as main memories therefore, respectively. In responding to an I/O instruction issued by a running one of said plural OSs, an address of said main memory assigned to said running OS which participates in an I/Oo operation requested by said I/O instruction is determined without intervention of the control program, and the address is translated into an address of the main storage of the computer system without intervention of said control program. The I/O operation is then executed by using the address resulting from said address translation.
    Type: Grant
    Filed: March 16, 1992
    Date of Patent: February 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Hidenori Umeno, Takashige Kubo, Nobutaka Hagiwara, Hiroaki Sato, Hideo Sawamoto, Taro Inoue, Shunji Tanaka
  • Patent number: 5386565
    Abstract: An OS control method for controlling an operating system (OS) running in a computer system on which a plurality of OSs run and which includes an instruction processor, a control program for controlling running of a plurality of OSs, a main storage, an external storage device, and an address translation circuit. In the course of processing performed by the instruction processor, predetermined operation of the instruction processor is monitored to output trace data affixed with an address conforming to the running OS in accordance with predetermined conditions for the predetermined operation. Address for the running OS is translated into a real address on the main storage. A debugging assist unit outputs trace data to one of plural storing areas of the main storage corresponding to the running OS at the translated real address.
    Type: Grant
    Filed: January 11, 1991
    Date of Patent: January 31, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Shunji Tanaka, Takayoshi Asai, Taro Inoue, Hidenori Umeno, Tsuyoshi Watanabe
  • Patent number: D504638
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: May 3, 2005
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Shunji Tanaka, Seiichi Ino, Naoki Hashimoto
  • Patent number: D511317
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: November 8, 2005
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Shunji Tanaka, Seiichi Ino, Naoki Hashimoto
  • Patent number: D511583
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: November 15, 2005
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Shunji Tanaka, Seiichi Ino, Naoki Hashimoto
  • Patent number: D515487
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: February 21, 2006
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Shunji Tanaka, Seiichi Ino, Naoki Hashimoto
  • Patent number: D517958
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: March 28, 2006
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Norikazu Matsumura, Keishi Fukumoto, Shunji Tanaka
  • Patent number: D520414
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: May 9, 2006
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Shunji Tanaka, Seiichi Ino, Tsutomu Shimizugami
  • Patent number: D522415
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: June 6, 2006
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Shunji Tanaka, Seiichi Ino, Naoki Hashimoto
  • Patent number: D526249
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: August 8, 2006
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Shunji Tanaka, Seiichi Ino, Naoki Hashimoto